Second page done. I managed to import BLOCK DIAGRAM from PDF thru SVG conversion, still required tons of manual text input
This sounds interesting, what tool for pdf conversion do you use? It's some kicad plugin or indep. tool? Can in OCR also scanned pdfs or only some modern with vectors?
but hey, industrial grade autism helped me do it while watching some amateur racing
Yeah, Normal is not the norm
It's just a uniform (we are the others)😀
Yes kicad is rapidly developing but it cause comaptability problems. I hope they will support in future all old formats. I use AD at work and also older version for my hobby projects and it works well together. But I have problems with some new kicad projects that I try to import in AD via kicad import plugin that it completly mess the schematic. Pcb layout design files imported mostly ok , needing only minor changes. I hope AD will update it soon. But it would be nice if kacaders also exported older format for compatability...
Random thought on clocks.
I'm pretty sure conventional wisdom is that AGP is a ratio of fsb.
Looking at everything I have, I'm pretty sure it's actually pci*2.
It makes no sense that the chipset has a 1:1 ratio for 66, and changes automatically at 100+ to 2/3.
It's always exactly 2xpci. Which is driven by a click chip. Best I can tell the only chip that isn't from a clock gen is the agp.
Which is why some later boards had a 133 fsb with 66pci - because they were setting the correct pci clock. There was no sudden magical 1/2 divider. It was a fsb /4 (pci) *2 =agp.
It also makes me wonder if the clocks can be driven by completely different sources without any respect for ratios and still work.
I'm particularly curious how it would go if GCLKOUT was grounded/floating, but GCLKIN and the agp slot were driven by a separate source. Would it crack the shits or just work?
This sounds interesting, what tool for pdf conversion do you use? It's some kicad plugin or indep. tool? Can in OCR also scanned pdfs or only some modern with vectors?
INTEL MODEL 440BX.pdf has vector representation of block diagram. I think some time ago you could have used ghostscript directly
mutool.exe convert -o dest.svg "INTEL MODEL 440BX.pdf" 2
text broken down into individual letters 😐
1<use data-text="R" xlink:href="#font_0_51"
but otherwise fine and imports into kicad no problem (without text)
inkscape -n 2 "INTEL MODEL 440BX.pdf" -o dest.svg
text into individual letters made up of vectors 😁millions of vectors😀 Just moving and trying to scale that import bogs down even ~fast computer. inkscape CLI has --export-text-to-path option doing complete opposite of what I want and no way of disabling it 😒 GUI conversion lets me substitute missing fonts (ArialNarrow, HelveticaNarrow) and produces nice text, grrr why cant I do this from CLI 😐 https://gitlab.com/inkscape/inbox/-/issues/3495 4 year old "HowTo Disable texts to paths for EMF output from CLI" https://bugs.launchpad.net/inkscape/+bug/1747696 6 year old "No command-line flag to disable text-to-path when exporting as WMF"
As a last resort I resigned myself to inkscape GUI as that was the only way of making it substitute fonts. Saving to svg gives vector output + text is whole sentences in <text> tags. Imports smoothly with minor glitch of kicad not understanding <text> elements at all 🙁 Apparently there is no way of importing text into eeschema. I resigned to manual entry instead of figuring out how to automate it. Shouldnt be too hard considering its this:
I also tried some online tools like https://convertio.co/pdf-svg/ This one is using inkscape under the hood, but somehow manages to invoke it without export-text-to-path?!?! Either they have some GUI automation or maybe older version did that by default. It also does much better job keeping text grouped and in its correct place. Produces best output, but converts only one pdf page at a time, so one needs something like this to extract one page
For pdfs with images the best I could find is xpdf-tools pdfimages, extracts all images raw with no conversions.
I had zero luck with OCR, even magical AI bullshit like https://llamaocr.com fails at the most trivial I-1 O-0 8-B cases, hallucinates a lot and substitutes perfectly readable text with "[Insert other elements here]" haha. Yes misted LLM overlord thats exactly what I wanted, I wanted you to order me around 😀
I'm particularly curious how it would go if GCLKOUT was grounded/floating, but GCLKIN and the agp slot were driven by a separate source. Would it crack the shits or just work?
GCLKIN looks like chipset internal PLL feedback. hmm intel datasheet "AGP Clock In: The GCLKIN input is a feedback reference from the GCLKOUT signal."
Its possible and likely that GCLKOUT is just a functionally separate clock source block and all the AGP logic happens according to GCLKIN.
Its possible but unlikely that GCLKOUT is derived from FSB HCLKIN.
Its very possible that GCLKOUT is just a clock doubled PCI PCLKIN.
if 1 and 3 are correct then just keeping PCI clock correct will make AGP happy. EDIT or maybe not? "AGP Bus Divider- A lingering problem" https://www.anandtech.com/show/574/4
Its surprising to me that intel would rather divide HCLKIN by 2/3 than clock double PCLKIN. I was wondering how teh Chipset knows and on page 11 there is a magic 10Kohm resistor connecting 100/66 PCU signal to MAB#12 - a boot config strap.
datasheet curious entry "Please make the GCLKIN trace length 3.3" more than the GCLKOUT recommended trace length. Stub to tee should be 1" MAX."
On P2B GCLKIN GCLKOUT are nicely routed next to chipset and it would be trivial to lift R60 and instead connect R60 R61 pads to BXPCLK for 33MHz AGP just for testing.
Yeah you're in the right track.
I'm pretty sure 25+years of wisdom is misunderstood.
The p3b-f uses the ICS9250-08.
This chip supports 2 versions of the 133fsb.
Pci=fsb/3 and pci=fsb/4
To prove or disprove the theory that GCLKOUT =pci*2 all we need is
* someone willing;
* with a stable 133fsb p3b-f (or similar) who can pick both options (softfsb?)
* and a scope on GCLKOUT
If GCLKOUT is 66 and 89, it's proven.
If GCLKOUT is 89 and 89, it's disproven
I'm moderately sure the additional length on GCLKIN is to estimate the attention at the card and compensate.
BTW with kicad imports only the brackets matter. New lines and white space between are irrelevant.
See the spreadsheet above. It can paste multiple pins/labels (most of the time) by filling in the first columns and just copy pasting the relevant column.
You might be able to adapt it for text import.
Pci=fsb/3 and pci=fsb/4
To prove or disprove the theory that GCLKOUT =pci*2 all we need is
sadly that was already checked 20 years ago as I linked https://www.anandtech.com/show/574/4 so Intel is dividing by 2/3 from FSB. Still its possible GCLKIN is true input and not just PLL feedback. True clock inputs are usually marked with a triangle on part footprint. GCLKIN does have a triangle like HCLKIN and PCLKIN. SDRAM controller has similar arrangement with DCLKO producing clock and DCLKWR marked as clock input supposedly a "feedback" but this time datasheet states "This clock is used by the 82443BX when writing data to the SDRAM array". Would be funny if we could make 440BX memory controller asynchronous to FSB. .. alas 815 datasheet describes this arrangement in more detail
>System Memory Delay Locked Loop (DLL) blocks that offset the
>transmit and receive clocks used to interface with the external SDRAM devices. The Transmit
>DLL provides an early version of SCLK to provide additional setup margin to the external
>SDRAM devices. The Receive DLL provides a late version of SCLK to provide additional setup
>time on read data driven by the SDRAM devices back to the GMCH.
and while 440BX reference diagram suggests linking both DCLKWR AD25 and DCLKRD AB22 to DCLKREF the datasheets has AB22 as NC and Asus boards dont connect that pin to anything. Either 440BX uses DCLKWR AD25 as sole input for mem controller clock, or more likely its really just a feedback to Delay Locked Loop and whole controller is running according to DCLKO ticks.
But I just dont understand AGP at all 😀 On BX AGP clock goes to both Chipset and AGP slot. on 815 it goes only to the slot directly from clockgen, chipset dgaf about clock? WTF no feedback no nothing. Both in real boards and in Intel reference designs.
BTW with kicad imports only the brackets matter. New lines and white space between are irrelevant.
Yes, I was worried about Text elements requiring uuids, but just did an experiment and it regenerates UUIDs on manually added elements 😀 so it is possible to fully import whole diagram from PDF including all the text 😮 will just require some sed regex magic.
It's when you have a whole row of 50 with different names and you're prone to typos that the spreadsheet is handy.
I guess it's possible the chipset doesn't actually need to make the clock and the clock on the bus only is just fine, but it was early days and they wanted to be cautious?
I suppose if someone motivated enough and bored enough wanted to check, the 2 resistors from GCLKOUT and GCLKIN could be removed and a bodge wire run from an empty pci clock pin to the agp clock pin to see what happens. Card works but slow =win. That makes it easy. Just a clock doubler on pci or similar.
On the 810e DCLKREF is 48mhz and is display interface clock. Ie it's probably to sync vga/lvds signals for onboard gfx.
I don't but they wrote it doesnt work on BX anyway... Oh, yes! They exist. But they don't work on BX boards as we already discussed here. 😢
Did someone make a pcb design of such slot1 adapter? I have also some older LX MB with slot1 and have some server S8 card that can donor the S8 socket...
And Pentium-M, I think it need at least P4 chipset, like 845 or 855 and even then it needs non-trivial bios hack. I got powerleap P-M adapter and put it to a P4 MB with 845. It hanged soon during post with just black screen. Microcode update didn't help. Then I got hacked bios and it boots but there's still some issue with reset that I need power cycle instead. So I don't see big chance on BX...
It was probably a voltage problem on bx.
The PPros needed 3+v which most didn't give.
Though, they should have given 2.8 for the early p2s which you'd think would be enough for a post.
If you have the adapter and the volts ppro should work in any slot 1 board. Re: Socket 8 --> Slot 1 Slotket Adapters
Theoretically a BX with a good vrm could support all the way from the PPro 150 3.3v to Tualatin 1.4ghz 1.65v. I don't see any real reason fsb underclocking with the right clock gen isn't an option either.
RayeRwrote on 2024-11-25, 14:05:I don't but they wrote it doesnt work on BX anyway...
Oh, yes! They exist. But they don't work on BX boards as we already discus […] Show full quote
I don't but they wrote it doesnt work on BX anyway... Oh, yes! They exist. But they don't work on BX boards as we already discussed here. 😢
Did someone make a pcb design of such slot1 adapter? I have also some older LX MB with slot1 and have some server S8 card that can donor the S8 socket...
And Pentium-M, I think it need at least P4 chipset, like 845 or 855 and even then it needs non-trivial bios hack. I got powerleap P-M adapter and put it to a P4 MB with 845. It hanged soon during post with just black screen. Microcode update didn't help. Then I got hacked bios and it boots but there's still some issue with reset that I need power cycle instead. So I don't see big chance on BX...
Let's put this to bed. PPro works perfectly fine on BX if your VRM can supply the correct voltage AND the BIOS doesn't crash on MSR writes
The attachment 20241117_171616.jpg is no longer available
It's the last half decent chipset that connects to the northbridge via pci and has isa. Plus it has an integrated superio, ata100, hardware soundblaster with alleged dos compatibility, hardware monitor and native 9x drivers.