Universal chipset patcher [Final 1.1.2 release + src].

Reply 20 of 24, by Rav

Posted on 2026-03-24, 17:50

Rav Offline

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Posts: 185
Joined: 2023-02-05, 05:42

aVd wrote on 2026-03-24, 13:06:

Hi, @Rav,
I just found, that I have a motherboard with ALi M1489/87 (FinALi-486) chipset - DataExpert EXP8449 rev. 1.2. What can I do with your Universal Chipset Patcher?

Thank you!

Well, I am not sure the current linked version of UCP work with 1489, as I look in the code and the version I have is pre-refactor.
That been said, I will refactor it so it compile with 1489 uncommented and post it here as the final release of UCP 1.x branch along with the source code.

As for what it can do, look at that code in this post (the // comments for each block).
I should have the final release in 24-48hr. Time to refactor that and also purge the crust that I added when I tried to do PCI Management Mode (it's 16 bits code and could not get it working using mixing with 32 bits asm code)...

As for UCP 2.0, it not a refactor, it's a full rebuild, in the form of a 32 bits dos application that is mainly menu driven ("slightly" inspired from Award bios). Chip maintenance in the new code is also a lot simpler

This is 1489 code I have to refactor

1#include "chipsets/chipset.h"
2#include <stdio.h>
3#include <stdlib.h>
4
5void init_ali1489(void);
6
7void init_ali1489(void){
8// Chipset Name
9    memcpy(chip_name, "ALI 1489/FINALi 486\0", sizeof("ALI 1489/FINALi 486\0"));
10
11// Ports
12    index_port = 0x0022;
13    data_port = 0x0023;
14
15// Chipset Unlock
16    unlock_reg = 0x03;
17    unlock_value = 0xC5;
18
19// Hidden Refresh
20    hr_reg = 0x12;
21    hr_mask = 0x7F;
22    memcpy(hr_text[0], "disabled\0", sizeof("disabled\0"));
23    hr_opt[0] = 0x00;
24    memcpy(hr_text[1], "enabled\0", sizeof("enabled\0"));
25    hr_opt[1] = 0x80;
26
27// Hidden Refresh time
28    hrtime_reg = 0x1A;
29    hrtime_mask = 0x3F;
30    memcpy(hrtime_text[0], "15us\0", sizeof("15us\0"));
31    hrtime_opt[0] = 0x00;
32    memcpy(hrtime_text[1], "30us\0", sizeof("30us\0"));
33    hrtime_opt[1] = 0x40;
34    memcpy(hrtime_text[2], "60us\0", sizeof("60us\0"));
35    hrtime_opt[2] = 0x80;
36    memcpy(hrtime_text[3], "120us\0", sizeof("120us\0"));
37    hrtime_opt[3] = 0xC0;
38
39// Cycle Check Point
40    ccp_reg = 0x15;
41    ccp_mask = 0xCF;
42    memcpy(ccp_text[1], "fast\0", sizeof("fast\0"));
43    ccp_opt[1] = 0x00;
44    memcpy(ccp_text[2], "normal\0", sizeof("normal\0"));
45    ccp_opt[2] = 0x10;
46    memcpy(ccp_text[3], "slow\0", sizeof("slow\0"));
47    ccp_opt[3] = 0x20;
48
49// TODO: Add Master Cycle Check Point
50
51// Change cache mode to Write-Through
52    wt_reg = 0x16;
53    wt_mask = 0xFB;
54    wt_opt[0] = 0x00;
55// Change cache mode to Write-Back
56    wb_reg = 0x16;
57    wb_mask = 0xFB;
58    wb_opt[0] = 0x04;
59
60// L2 8bit tag

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61    l2tag_reg = 0x16;
62    l2tag_mask = 0xF7;
63    memcpy(l2tag_text[0], "7bit\0", sizeof("7bit\0"));
64    l2tag_opt[0] = 0x00;
65    memcpy(l2tag_text[1], "8bit(Force Dirty)\0", sizeof("8bit(Force Dirty)\0"));
66    l2tag_opt[2] = 0x08;
67
68// L2 cache read wait states
69    l2r_reg = 0x16;
70    l2r_mask = 0xDF;
71
72    memcpy(l2r_text[0], "Fast\0", sizeof("Fast\0"));
73    l2r_opt[0] = 0x00;
74    memcpy(l2r_text[1], "Normal\0", sizeof("Normal\0"));
75    l2r_opt[1] = 0x20;
76
77// L2 cache write wait states
78    l2w_reg = 0x19;
79    l2w_mask = 0xEF;
80
81    memcpy(l2w_text[0], "Fast\0", sizeof("Fast\0"));
82    l2w_opt[0] = 0x00;
83    memcpy(l2w_text[1], "Normal\0", sizeof("Normal\0"));
84    l2w_opt[1] = 0x10;
85
86// hitmj
87    hitmj_reg = 0x19;
88    hitmj_mask = 0xFB;
89    memcpy(hitmj_text[2], "2t\0", sizeof("2t\0"));
90    hitmj_opt[2] = 0x00;
91    memcpy(hitmj_text[3], "3t\0", sizeof("3t\0"));
92    hitmj_opt[3] = 0x4;
93
94// EDO 2-1-1-1 timing
95    edo2111_reg = 0x1A;
96    edo2111_mask = 0xEF;
97
98    memcpy(edo2111_text[0], "Disabled\0", sizeof("Disabled\0"));
99    edo2111_opt[0] = 0x00;
100    memcpy(edo2111_text[1], "Enabled\0", sizeof("Enabled\0"));
101    edo2111_opt[1] = 0x10;
102
103// Memory Read Timing
104    ramr_reg = 0x1B;
105    ramr_mask = 0xFC;
106
107    memcpy(ramr_text[1], "fastest\0", sizeof("fastest\0"));
108    ramr_opt[1] = 0x03;
109    memcpy(ramr_text[2], "fast\0", sizeof("fast\0"));
110    ramr_opt[2] = 0x02;
111    memcpy(ramr_text[3], "slow\0", sizeof("slow\0"));
112    ramr_opt[3] = 0x01;
113    memcpy(ramr_text[4], "slowest\0", sizeof("slowest\0"));
114    ramr_opt[4] = 0x00;
115
116// Memory Write Timing
117    ramw_reg = 0x1B;
118    ramw_mask = 0xF3;
119
120    memcpy(ramw_text[1], "fastest\0", sizeof("fastest\0"));
121    ramw_opt[1] = 0x0C;
122    memcpy(ramw_text[2], "fast\0", sizeof("fast\0"));
123    ramw_opt[2] = 0x08;
124    memcpy(ramw_text[3], "slow\0", sizeof("slow\0"));
125    ramw_opt[3] = 0x04;
126    memcpy(ramw_text[4], "slowest\0", sizeof("slowest\0"));
127    ramw_opt[4] = 0x00;
128
129// ATBUS Divider
130    atbus_reg = 0x29;
131    atbus_mask = 0xF8;
132    memcpy(atbus_text[0], "7.16Mhz\0", sizeof("7.16Mhz\0"));
133    atbus_opt[0] = 0x00;
134    memcpy(atbus_text[1], "CLK/3\0", sizeof("CLK/3\0"));
135    atbus_opt[1] = 0x01;
136    memcpy(atbus_text[2], "CLK/4\0", sizeof("CLK/4\0"));
137    atbus_opt[2] = 0x02;
138    memcpy(atbus_text[3], "CLK/5\0", sizeof("CLK/5\0"));
139    atbus_opt[3] = 0x03;
140    memcpy(atbus_text[4], "CLK/6\0", sizeof("CLK/6\0"));
141    atbus_opt[4] = 0x04;
142    memcpy(atbus_text[5], "CLK/8\0", sizeof("CLK/8\0"));
143    atbus_opt[5] = 0x05;
144
145// ISA Command Wait time
146    isa16com_reg = 0x29;
147    isa16com_mask = 0x9F;
148    memcpy(isa16com_text[0], "0WS\0", sizeof("0WS\0"));
149    isa16com_opt[0] = 0x00;
150    memcpy(isa16com_text[1], "1WS\0", sizeof("1WS\0"));
151    isa16com_opt[1] = 0x20;
152    memcpy(isa16com_text[2], "2WS\0", sizeof("2WS\0"));
153    isa16com_opt[2] = 0x40;
154    memcpy(isa16com_text[3], "3WS\0", sizeof("3WS\0"));
155    isa16com_opt[3] = 0x60;
156
157// IO Recovery
158    iore_reg = 0x2A;
159    iore_mask = 0xFE;
160    memcpy(iore_text[0], "Disabled\0", sizeof("Disabled\0"));
161    iore_opt[0] = 0x00;
162    memcpy(iore_text[1], "Enabled\0", sizeof("Enabled\0"));
163    iore_opt[1] = 0x01;
164
165// IO Recovery Time
166    ioretime_reg = 0x2A;
167    ioretime_mask = 0xF1;
168    memcpy(ioretime_text[0], "0us\0", sizeof("0us\0"));
169    ioretime_opt[0] = 0x00;
170    memcpy(ioretime_text[1], "0.5us\0", sizeof("0.5us\0"));
171    ioretime_opt[1] = 0x02;
172    memcpy(ioretime_text[2], "1us\0", sizeof("1us\0"));
173    ioretime_opt[2] = 0x04;
174    memcpy(ioretime_text[3], "1.5us\0", sizeof("1.5us\0"));
175    ioretime_opt[3] = 0x06;
176    memcpy(ioretime_text[4], "2us\0", sizeof("2us\0"));
177    ioretime_opt[4] = 0x08;
178    memcpy(ioretime_text[5], "2.5us\0", sizeof("2.5us\0"));
179    ioretime_opt[5] = 0x0A;
180    memcpy(ioretime_text[6], "3us\0", sizeof("3us\0"));
181    ioretime_opt[6] = 0x0C;
182    memcpy(ioretime_text[7], "3.5us\0", sizeof("3.5us\0"));
183    ioretime_opt[7] = 0x0E;
184
185// Slow Refresh
186    sl_reg = 0x2A;
187    sl_mask = 0x9F;
188    memcpy(sl_text[0], "15us\0", sizeof("15us\0"));
189    sl_opt[0] = 0x00;
190    memcpy(sl_text[1], "30us\0", sizeof("30us\0"));
191    sl_opt[1] = 0x20;
192    memcpy(sl_text[2], "60us\0", sizeof("60us\0"));
193    sl_opt[2] = 0x40;
194    memcpy(sl_text[3], "120us\0", sizeof("120us\0"));
195    sl_opt[3] = 0x60;
196}

This is 1429 code that is current in the available build

1#include "chipsets/chipset.h"
2#include "chipsets/ali1429.h"
3#include <stdio.h>
4#include <stdlib.h>
5
6void init_ali1429(void){
7    int z = 0;
8// Chipset Name
9    memcpy(chip_name, "ALI 1429/G\0", sizeof("ALI 1429/G\0"));
10
11// Ports
12    index_port = 0x0022;
13    data_port = 0x0023;
14
15// Chipset Unlock
16    unlock_reg = 0x03;
17    unlock_value = 0xC5;
18
19// Memory Read Timing
20    memcpy(fnt_text[z], "Memory Read Timing\0", sizeof("Memory Read Timing\0"));
21    memcpy(fnt_switch[z], "/ramr\0", sizeof("/ramr\0"));
22
23    reg[z] = 0x16;
24    mask[z] = 0xFC;
25
26    memcpy(opt_text[z][1], "fastest\0", sizeof("fastest\0"));
27    opt[z][1] = 0x03;
28    memcpy(opt_text[z][2], "fast\0", sizeof("fast\0"));
29    opt[z][2] = 0x02;
30    memcpy(opt_text[z][3], "slow\0", sizeof("slow\0"));
31    opt[z][3] = 0x01;
32    memcpy(opt_text[z][4], "slowest\0", sizeof("slowest\0"));
33    opt[z][4] = 0x00;
34
35    z++;
36
37// Memory Write Timing
38    memcpy(fnt_text[z], "Memory Write Timing\0", sizeof("Memory Write Timing\0"));
39    memcpy(fnt_switch[z], "/ramw\0", sizeof("/ramw\0"));
40
41    reg[1] = 0x16;
42    mask[1] = 0xF3;
43
44    memcpy(opt_text[z][1], "fastest\0", sizeof("fastest\0"));
45    opt[z][1] = 0x0C;
46    memcpy(opt_text[z][2], "fast\0", sizeof("fast\0"));
47    opt[z][2] = 0x08;
48    memcpy(opt_text[z][3], "slow\0", sizeof("slow\0"));
49    opt[z][3] = 0x04;
50    memcpy(opt_text[z][4], "slowest\0", sizeof("slowest\0"));
51    opt[z][4] = 0x00;
52
53    z++;
54
55// L2 cache read wait states
56    memcpy(fnt_text[z], "L2 cache read wait states\0", sizeof("L2 cache read wait states\0"));
57    memcpy(fnt_switch[z], "/l2r\0", sizeof("/l2r\0"));
58
59    reg[z] = 0x19;
60    mask[z] = 0xBF;

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61
62    memcpy(opt_text[z][0], "0 WS\0", sizeof("0 WS\0"));
63    opt[z][0] = 0x00;
64    memcpy(opt_text[z][1], "1 WS\0", sizeof("1 WS\0"));
65    opt[z][1] = 0x40;
66
67    z++;
68
69// L2 cache write wait states
70    memcpy(fnt_text[z], "L2 cache write wait states\0", sizeof("L2 cache write wait states\0"));
71    memcpy(fnt_switch[z], "/l2w\0", sizeof("/l2w\0"));
72
73    reg[z] = 0x19;
74    mask[z] = 0xDF;
75
76    memcpy(opt_text[z][0], "0 WS\0", sizeof("0 WS\0"));
77    opt[z][0] = 0x00;
78    memcpy(opt_text[z][1], "1 WS\0", sizeof("1 WS\0"));
79    opt[z][1] = 0x20;
80
81    z++;
82
83// Hidden Refresh
84    memcpy(fnt_text[z], "Hidden Refresh\0", sizeof("Hidden Refresh\0"));
85    memcpy(fnt_switch[z], "/hr\0", sizeof("/hr\0"));
86
87    reg[z] = 0x12;
88    mask[z] = 0xEF;
89    memcpy(opt_text[z][0], "disabled\0", sizeof("disabled\0"));
90    opt[z][0] = 0x00;
91    memcpy(opt_text[z][1], "enabled\0", sizeof("enabled\0"));
92    opt[z][1] = 0x10;
93
94    z++;
95
96// hitmj
97    memcpy(fnt_text[z], "HITMJ sampling rate\0", sizeof("HITMJ sampling rate\0"));
98    memcpy(fnt_switch[z], "/hitmj\0", sizeof("/hitmj\0"));
99
100    reg[z] = 0x17;
101    mask[z] = 0xCF;
102    memcpy(opt_text[z][2], "2t\0", sizeof("2t\0"));
103    opt[z][2] = 0x00;
104    memcpy(opt_text[z][3], "3t\0", sizeof("3t\0"));
105    opt[z][3] = 0x10;
106    memcpy(opt_text[z][4], "4t\0", sizeof("4t\0"));
107    opt[z][4] = 0x20;
108    memcpy(opt_text[z][5], "5t\0", sizeof("5t\0"));
109    opt[z][5] = 0x30;
110
111    z++;
112// Cycle Check Point
113    memcpy(fnt_text[z], "Cycle Check Point\0", sizeof("Cycle Check Point\0"));
114    memcpy(fnt_switch[z], "/ccp\0", sizeof("/ccp\0"));
115
116    reg[z] = 0x17;
117    mask[z] = 0xFC;
118    memcpy(opt_text[z][1], "fast\0", sizeof("fast\0"));
119    opt[z][1] = 0x01;
120    memcpy(opt_text[z][2], "normal\0", sizeof("normal\0"));
121    opt[z][2] = 0x02;
122    memcpy(opt_text[z][3], "slow\0", sizeof("slow\0"));
123    opt[z][3] = 0x03;
124
125    z++;
126// RAS to CAS delay
127    memcpy(fnt_text[z], "RAS to CAS delay\0", sizeof("RAS to CAS delay\0"));
128    memcpy(fnt_switch[z], "/rtc\0", sizeof("/rtc\0"));
129
130    reg[z] = 0x1A;
131    mask[z] = 0x3F;
132    memcpy(opt_text[z][2], "2t\0", sizeof("2t\0"));
133    opt[z][2] = 0x00;
134    memcpy(opt_text[z][4], "4t\0", sizeof("4t\0"));
135    opt[z][4] = 0x40;
136    memcpy(opt_text[z][6], "6t\0", sizeof("6t\0"));
137    opt[z][6] = 0x80;
138
139    z++;
140// VESA Master Cycle ADSJ
141    memcpy(fnt_text[z], "VESA Master Cycle ADSJ\0", sizeof("VESA Master Cycle ADSJ\0"));
142    memcpy(fnt_switch[z], "/vesamcadsj\0", sizeof("/vesamcadsj\0"));
143
144    reg[z] = 0x1E;
145    mask[z] = 0xEF;
146    memcpy(opt_text[z][0], "normal\0", sizeof("normal\0"));
147    opt[z][0] = 0x00;
148    memcpy(opt_text[z][1], "delay\0", sizeof("delay\0"));
149    opt[z][1] = 0x10;
150
151    z++;
152// VESA L2 Cache Read
153    memcpy(fnt_text[z], "VESA L2 Cache Read wait\0", sizeof("VESA L2 Cache Read wait\0"));
154    memcpy(fnt_switch[z], "/vesal2r\0", sizeof("/vesal2r\0"));
155
156    reg[z] = 0x1E;
157    mask[z] = 0xF7;
158    memcpy(opt_text[z][0], "normal\0", sizeof("normal\0"));
159    opt[z][0] = 0x00;
160    memcpy(opt_text[z][1], "long\0", sizeof("long\0"));
161    opt[z][1] = 0x08;
162
163    z++;
164// VESA L2 Cache Write
165    memcpy(fnt_text[z], "VESA L2 Cache Write wait\0", sizeof("VESA L2 Cache Write wait\0"));
166    memcpy(fnt_switch[z], "/vesal2w\0", sizeof("/vesal2w\0"));
167
168    reg[z] = 0x1E;
169    mask[z] = 0xFB;
170    memcpy(opt_text[z][0], "normal\0", sizeof("normal\0"));
171    opt[z][0] = 0x00;
172    memcpy(opt_text[z][1], "long\0", sizeof("long\0"));
173    opt[z][1] = 0x04;
174
175    z++;
176// ATBUS Divider
177    memcpy(fnt_text[z], "ATBUS Divider\0", sizeof("ATBUS Divider\0"));
178    memcpy(fnt_switch[z], "/atbus\0", sizeof("/atbus\0"));
179
180    reg[z] = 0x20;
181    mask[z] = 0xF8;
182    memcpy(opt_text[z][0], "7.19Mhz\0", sizeof("7.19Mhz\0"));
183    opt[z][0] = 0x00;
184    memcpy(opt_text[z][1], "CLK/4\0", sizeof("CLK/4\0"));
185    opt[z][1] = 0x01;
186    memcpy(opt_text[z][2], "CLK/5\0", sizeof("CLK/5\0"));
187    opt[z][2] = 0x02;
188    memcpy(opt_text[z][3], "CLK/6\0", sizeof("CLK/6\0"));
189    opt[z][3] = 0x03;
190    memcpy(opt_text[z][4], "CLK/8\0", sizeof("CLK/8\0"));
191    opt[z][4] = 0x04;
192    memcpy(opt_text[z][5], "CLK/10\0", sizeof("CLK/10\0"));
193    opt[z][5] = 0x05;
194    memcpy(opt_text[z][6], "CLK/12\0", sizeof("CLK/12\0"));
195    opt[z][6] = 0x06;
196
197    z++;
198// Pooling Clock
199    memcpy(fnt_text[z], "Pooling Clock\0", sizeof("Pooling Clock\0"));
200    memcpy(fnt_switch[z], "/pollclock\0", sizeof("/pollclock\0"));
201
202    reg[z] = 0x20;
203    mask[z] = 0x8F;
204    memcpy(opt_text[z][0], "14.318Mhz\0", sizeof("14.318Mhz\0"));
205    opt[z][0] = 0x00;
206    memcpy(opt_text[z][1], "CLK\0", sizeof("CLK\0"));
207    opt[z][1] = 0x10;
208    memcpy(opt_text[z][2], "CLK/2\0", sizeof("CLK/2\0"));
209    opt[z][2] = 0x20;
210    memcpy(opt_text[z][3], "CLK/3\0", sizeof("CLK/3\0"));
211    opt[z][3] = 0x30;
212    memcpy(opt_text[z][4], "CLK/4\0", sizeof("CLK/4\0"));
213    opt[z][4] = 0x40;
214    memcpy(opt_text[z][5], "28.636Mhz\0", sizeof("28.636Mhz\0"));
215    opt[z][5] = 0x50;
216
217    z++;
218// ISA Write Cycle
219    memcpy(fnt_text[z], "ISA write cycle\0", sizeof("ISA write cycle\0"));
220    memcpy(fnt_switch[z], "/isaws\0", sizeof("/isaws\0"));
221
222    reg[z] = 0x22;
223    mask[z] = 0xFB;
224    memcpy(opt_text[z][0], "0 WS\0", sizeof("0 WS\0"));
225    opt[z][0] = 0x00;
226    memcpy(opt_text[z][1], "1 WS\0", sizeof("1 WS\0"));
227    opt[z][1] = 0x04;
228
229    z++;
230// Onboard IO Recovery
231    memcpy(fnt_text[z], "Onboard IO Recovery\0", sizeof("Onboard IO Recovery\0"));
232    memcpy(fnt_switch[z], "/oiore\0", sizeof("/oiore\0"));
233
234    reg[z] = 0x22;
235    mask[z] = 0xFD;
236    memcpy(opt_text[z][0], "Disabled\0", sizeof("Disabled\0"));
237    opt[z][0] = 0x00;
238    memcpy(opt_text[z][1], "Enabled\0", sizeof("Enabled\0"));
239    opt[z][1] = 0x02;
240
241    z++;
242// IO Recovery
243    memcpy(fnt_text[z], "IO Recovery\0", sizeof("IO Recovery\0"));
244    memcpy(fnt_switch[z], "/iore\0", sizeof("/iore\0"));
245
246    reg[z] = 0x22;
247    mask[z] = 0xFE;
248    memcpy(opt_text[z][0], "Disabled\0", sizeof("Disabled\0"));
249    opt[z][0] = 0x00;
250    memcpy(opt_text[z][1], "Enabled\0", sizeof("Enabled\0"));
251    opt[z][1] = 0x01;
252
253    z++;
254// 32Bits ISA Wait Time
255    memcpy(fnt_text[z], "32Bits ISA Wait Time\0", sizeof("32Bits ISA Wait Time\0"));
256    memcpy(fnt_switch[z], "/isa32wt\0", sizeof("/isa32wt\0"));
257    reg[z] = 0x25;
258    mask[z] = 0x3F;
259    memcpy(opt_text[z][2], "2t\0", sizeof("2t\0"));
260    opt[z][2] = 0x00;
261    memcpy(opt_text[z][4], "4t\0", sizeof("4t\0"));
262    opt[z][4] = 0x40;
263    memcpy(opt_text[z][6], "6t\0", sizeof("6t\0"));
264    opt[z][6] = 0x80;
265    memcpy(opt_text[z][8], "8t\0", sizeof("8t\0"));
266    opt[z][8] = 0xC0;
267
268    z++;
269// ISA Mem Command Wait Time
270    memcpy(fnt_text[z], "16 bits ISA Memory Command Wait Time\0", sizeof("16 bits ISA memory Command Wait Time\0"));
271    memcpy(fnt_switch[z], "/isa16wt\0", sizeof("/isa16wt\0"));
272    reg[z] = 0x25;
273    mask[z] = 0xF3;
274    memcpy(opt_text[z][0], "0WS\0", sizeof("0WS\0"));
275    opt[z][0] = 0x00;
276    memcpy(opt_text[z][1], "1WS\0", sizeof("1WS\0"));
277    opt[z][1] = 0x04;
278    memcpy(opt_text[z][2], "2WS\0", sizeof("2WS\0"));
279    opt[z][2] = 0x08;
280    memcpy(opt_text[z][3], "3WS\0", sizeof("3WS\0"));
281    opt[z][3] = 0x0C;
282    
283    z++;
284// ISA Command Wait time
285    memcpy(fnt_text[z], "16 bits ISA Command Wait time\0", sizeof("16 bits ISA Command Wait time\0"));
286    memcpy(fnt_switch[z], "/isa16com\0", sizeof("/isa16com\0"));
287
288    reg[z] = 0x25;
289    mask[z] = 0xFC;
290    memcpy(opt_text[z][0], "0WS\0", sizeof("0WS\0"));
291    opt[z][0] = 0x00;
292    memcpy(opt_text[z][1], "1WS\0", sizeof("1WS\0"));
293    opt[z][1] = 0x01;
294    memcpy(opt_text[z][2], "2WS\0", sizeof("2WS\0"));
295    opt[z][2] = 0x02;
296    memcpy(opt_text[z][3], "3WS\0", sizeof("3WS\0"));
297    opt[z][3] = 0x03;
298
299    z++;
300// Slow Refresh
301    memcpy(fnt_text[z], "Slow Refresh\0", sizeof("Slow Refresh\0"));
302    memcpy(fnt_switch[z], "/sl\0", sizeof("/sl\0"));
303    reg[z] = 0x25;
304    mask[z] = 0xCF;
305    memcpy(opt_text[z][0], "Disabled\0", sizeof("Disabled\0"));
306    opt[z][0] = 0x00;
307    memcpy(opt_text[z][1], "30us\0", sizeof("30us\0"));
308    opt[z][1] = 0x10;
309    memcpy(opt_text[z][2], "60us\0", sizeof("60us\0"));
310    opt[z][2] = 0x20;
311    memcpy(opt_text[z][3], "120us\0", sizeof("120us\0"));
312    opt[z][3] = 0x30;
313
314    z++;
315// Change cache mode to Write-Through
316    wt_reg = 0x19;
317    wt_mask = 0xF7;
318    wt_opt[0] = 0x00;
319// Change cache mode to Write-Back
320    wb_reg = 0x19;
321    wb_mask = 0xF7;
322    wb_opt[0] = 0x08;
323}

Reply 21 of 24, by Rav

Posted on 2026-03-24, 18:57

Rav Offline

Rank Member

Rank: Member
Posts: 185
Joined: 2023-02-05, 05:42

aVd wrote on 2026-03-24, 13:06:

Hi, @Rav,
I just found, that I have a motherboard with ALi M1489/87 (FinALi-486) chipset - DataExpert EXP8449 rev. 1.2. What can I do with your Universal Chipset Patcher?

Thank you!

I have just updated the first post of the thread with the final release of the 1.x real mode branch, including source code.
It should now work properly with Ali 1489. As for the supported functions, you can see the screenshot.

The attachment ali1489.jpg is no longer available

Reply 22 of 24, by aVd

Posted on 2026-03-24, 20:16

aVd Offline

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Rank: Member
Posts: 107
Joined: 2026-02-21, 10:26
Location: Europe

Ok, I got it. Seems like very handy tool for fine tuning of RAM, Cache and ISA settings.

Thank you very much for sharing the new real mode version with ALi M1489/87 chipset support and its source code, @Rav! I'll try to compile UCP 1.1.2 with Borland C++ 3.1.

DOS fan :: artificial "intelligence" - not a fan... not a fan at all :: is freeware a lie, when human freedom is a fundamental lie?

Reply 23 of 24, by Rav

Posted on 2026-03-24, 22:23

Rav Offline

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Rank: Member
Posts: 185
Joined: 2023-02-05, 05:42

aVd wrote on 2026-03-24, 20:16:

Ok, I got it. Seems like very handy tool for fine tuning of RAM, Cache and ISA settings.

Thank you very much for sharing the new real mode version with ALi M1489/87 chipset support and its source code, @Rav! I'll try to compile UCP 1.1.2 with Borland C++ 3.1.

Good luck!

Note : I did begin the project using Borland C++ 4.5 And compiled it successfully with 5.02 (That include the last build, but it should still compile on 4.5). I never tested with 3.1.

Reply 24 of 24, by aVd

Posted on Yesterday, 10:25

aVd Offline

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Rank: Member
Posts: 107
Joined: 2026-02-21, 10:26
Location: Europe

Rav wrote on 2026-03-24, 22:23:

Good luck!

Note : I did begin the project using Borland C++ 4.5 And compiled it successfully with 5.02 (That include the last build, but it should still compile on 4.5). I never tested with 3.1.

Hi,
There's no problem to be compiled with Borland C++ version 3.1, except that I still get some #define-mess linker errors. So far more than 25+ linker errors like "Linker Error: _readctc defined in module UCP.C is duplicated in module CACHETST.C".

Also, "doCacheTest" function in "chipset.c" is left empty. Seems like it's unused in the rest of the code. There's a problem with "print_done" function (from "utils.c") usage in "ucp.c". Plus some minor redundant code lines here and there.

Is far as I know Borland C++ versions 4.5 and 5.02 are win 3.1+ and win 95 based, so I can't use them.

DOS fan :: artificial "intelligence" - not a fan... not a fan at all :: is freeware a lie, when human freedom is a fundamental lie?

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