Here are the components from the previously uploaded version. Are these the ones you want to use?

(Pay no mind to board size/shape/component position. Still in flux.)

Though, if you have any preference whatsoever what side gets the parts, now is the time to tell me.

Blavius wrote on 2022-09-11, 06:07:

Sphere478 wrote on 2022-09-10, 19:46:

If someone wants to post kicad footprints with nets of the two sockets, I might tinker with this a little. (If it is welcome)

No promises,

I’m thinking pin header stack. Two double layer pcbs probably.

You can find the netted circuit and footprints in the attached project. It would be great to have someone with more experience look at this.

Taking a closer look at what you did here the power planes appear to be kinda messed up. The signal trace routing looks relatively tidy and straightforward though for a two layer layout, good job. It could probably have been improved using four layers. Not bad, power planes need some tweaking though a few sections don’t appear to be connected? 😀 not claiming to be an authority, just some stuff that pops out. Good job, I can tell you put some work into it 😀

Btw, it seems like you may understand some of the jdec standards a little better than I and possibly how to do some signaling considerations/testings that I have some gaps in. Obviously I’m nowhere close to a final draft here but if you have any observations or suggestions lemme know.

feipoa wrote on 2022-09-12, 03:50:

I recall we've discussed this to some extent in this thread. I don't fully understand the whole 286/386 FSB scheme. On all my 386 boards, if I am running a 100 MHz crystal oscillator, for example, the FSB is 50 MHz, or half the crystal osc. However, in the past, when I've measured the frequency going into the CPU, I recorded 100 MHz. So do 386 CPUs normally halve the incoming frequency? And clock doubling CPUs merely not halve it? If the later, then the freq. on the PCB would be 100 MHz. Or maybe the scope was seeing more than one frequency superimposed, e.g. 50 Mhz and 100 Mhz and I just saw the 100 Mhz freq, not looking for the 50 Mhz freq? I don't know. 286's are weird like this as well. On my 286, if there's a 100 MHz crystal oscillator installed, the FSB is 25 MHz, or quarters the crystal osc. For the interposer, best case, the FSB on the interposer would be 50 Mhz, worst case 100 Mhz. Maybe someone else could answer this better? Does planning for 80 or 100 Mhz complicate things with the layout requirements?

Yes the 286 and 368 halve the incoming clock signal. This does not mean that the buses between the CPU and motherboard (FSB) actually transfer at the same speed as the clock pin. They are still only changing on every other clock pulse.

In the case of the 286 with the 4x oscillator, either the chipset or a PAL is halving the oscillator clock before it gets to the CPU (where it is halved again internally).

Bottom line with the 286 and 386 is the FSB is always the same as the CPU's actual speed regardless of the oscillator frequency. This does not apply to "upgrade" CPUs with internal clock doubling. Their buses are 1/2 the clock doubled core.

For the PCB I would use 4 layers as JLCPCB can manufacture it for a nice price, only 8$ (4L) vs 2$ (2L) but adding a shipping cost it doesn't matter. Everything above 4-layers gets much more expansive. For vias you can use 0.2mm holes (helps a lot compared to common 0.3mm holes) and trace width/clearance could be 4/4mil if I remember...

RayeR wrote on 2022-09-12, 19:08:

For the PCB I would use 4 layers as JLCPCB can manufacture it for a nice price, only 8$ (4L) vs 2$ (2L) but adding a shipping cost it doesn't matter. Everything above 4-layers gets much more expansive. For vias you can use 0.2mm holes (helps a lot compared to common 0.3mm holes) and trace width/clearance could be 4/4mil if I remember...

If 4 layer is even possible on this project for the through hole stack style, it seems like it will come with significant sacrifices to flood quality on the power layers and probably signal interference.

I think that this old devices at relative low speeds are not such sensitive to signal integrity, esp. on such kind of interposer with relative short traces. Also traces length tuning doesn't make sense here, I did it e.g. for DDR3 memory routing but not here, I doubt that designer of the 386 MB tuned lengths too...

R1 (goes between Vout and ADJ) on MIC29302WT would be a through-hole trim pot, like PV36W102C01B00, https://www.digikey.com/en/products/detail/bo … 02C01B00/666501 Only two through-holes needed. Your drawing shows SMD pads.

R2, 121-ohm, SMD size 0805 is fine.

Cin/Cout can be SMD, perhaps 593D106X9016C2TE3 , which is SMD 2312 size and 450mOhm. Size can go smaller at the expense of higher ESR, e.g. TR3A106K010C0900 is 1206 size and 900 mOhm. I'm not sure if you will add multiple Vcc3 caps. I see some interposers might use 8x 10uF parallel caps (Evergreen Am5x86 interposer), while others just use 1x 10uF (Evergreen BL3 interposer).

What is JP1 ? An option to bypass the VRM if running a 5V SXL chip?

feipoa wrote on 2022-09-12, 20:32:

R1 (goes between Vout and ADJ) on MIC29302WT would be a through-hole trim pot, like PV36W102C01B00, https://www.digikey.com/en/products/detail/bo … 02C01B00/666501 Only two through-holes needed. Your drawing shows SMD pads.

R2, 121-ohm, SMD size 0805 is fine.

Cin/Cout can be SMD, perhaps 593D106X9016C2TE3 , which is SMD 2312 size and 450mOhm. Size can go smaller at the expense of higher ESR, e.g. TR3A106K010C0900 is 1206 size and 900 mOhm. I'm not sure if you will add multiple Vcc3 caps. I see some interposers might use 8x 10uF parallel caps (Evergreen Am5x86 interposer), while others just use 1x 10uF (Evergreen BL3 interposer).

Thoughts on this layout? I can probably find room for more caps

I gave the fan its own header,

And took the isa signal out of it and give it it’s own pin? How does this sound?

What is JP1 ? An option to bypass the VRM if running a 5V SXL chip?

appears so, seems handy? Keep it?

Some more playing around with layout. I can also add capacitor pads to the underside but keep in mind all these caps will need to have vias around them to connect to their respective power layers, which will take up more space.

As you can see I played around with the pink layer a bit optimizing it, looks pretty good. Probably do that with all layers, take a look at routing then go back and do them all again. More I play with it, the cleaner and shorter the routing will get, but overall most won’t get a whole lot shorter/better. But getting that last bit takes a while.

Btw, can you give me a measurement from the center of a pin to the edge of the chip on your large chip we are adapting to? Need this in precise detail, exact measurement then suggest additional clearance you recommend beyond that. Need to know how close to the chip I can put these components.

The goal is to get that overhang as narrow as possible to increase the number of motherboards this can be used in. Sometimes motherboard have stuff in the way around the socket. Personally, I don't envision anyone wanting to use a 5V SXL in here, so I think ditch the bypass jumper. Isolating MEMW and creating a dedicated fan header is fine, but it would ideally be a 2-pin fan header. I don't know any 386 motherboard with a tach to make use of the 3rd pin. I've only ever seen 386 and 486 upgrade units, which even have fan headers, having 2-pin headers.

I think shrinking the overhang is more important than ESR, so if it saves space, I'd replace those caps to 1206. However, keep in mind that you can also place flatish SMD items on the underside of the overhang. If I had to guess, looking at the Evergreen QFP144 SXL2-66 upgrade, they are using 1206 tantalums. But notice how they aren't right next to the VRM (photo on page 12)? They are maybe 2 cm away.

To further save space, there should be a variant of the VRM with straight pins, however looking at availablity on digikey and mouser, I only see MIC29302AWD, with the rest on order, not expected for a year. MIC29302AWD looks to be surface mount TO-252-5, but pins spaced 1.143 - 1.397 mm. This would make the overhang too long.

I'm not sure why the previous posters MIC29302WT has two rows of pins. Looking online, I see what looks like a single row with 2.53 mm spacing. https://www.ebay.com/itm/121373209020 I think this is TO-247 as determined from page 33 of the datasheet for MIC29302 (attached). Not sure why the eBay listing says TO-220. What's the difference? EDIT: 2.53 mm for TO-247 and 1.70 mm for TO-220. The image on eBay, if I had to guess, is TO-220, so 1.70 mm spacing. Perhaps I should order one and measure before any PCB gets printed?

For the distance from the centre of an edge pin of a PGA-168 to the far edge of the factory heatsink, it is nominally 2.00 mm. However, the heatsinks weren't always completely centred. I measured the 4 sides of my unit and got between 1.9 mm to 2.1 mm.

The 5v option:
At the moment removing that part won’t help me make it any more narrow, should I just leave it for now? Your call, if you want it off I’ll take it off. Just seems like we should be able to find room for it, kinda a free feature ya know?

Can you tell me which side will have the most room on most motherboards? Is there any kinda bias there?

I can make it as thin as the widest part, and move some parts to other sides, and put capacitors maybe in the middle.

The side that juts out doesn’t have to be flat, we can have it just pop out for one part.

I’m in the middle of running some errands right now and will have to type the rest of this reply later. And look into your ideas with the parts when I get home.

Feel free to sketch out your ideas on paper btw, layout wise. Drawings help a lot.

We can also modify the fet footprint and bend it when installing

Okay, I found a vertical footprint for the regulator and it has 0.0668" spacing which falls between min/max on datasheet,

I added a outline for two pin fan header inside the 3 pin header. (best of both worlds?)

here is a new layout to ponder:

I don’t like having those vias so close to solder pads, will see about moving them farther away. (Solder bridging risk)

I’m moving those around and cleaning up the blue layer a bit as we speak. Lots of cleanup to do… lots… spaghetti! I tell you! Hahah

Cool!

When I built my first prototype, I remember looking into the zone surrounding the PGA-132 socket on my 386 boards and noting that there wasn't any particular side which had less clutter around it compared to the others. Perhaps the best course here is to follow the placement of the overhang to that of the commercial product I showed on page 12. Perhaps they did some kind of review on this matter. Probably would also be a good idea to identify (silk screen) pin 1 for the both PGA-132 and PGA-168 sockets.

If there's space for JP1, I guess just include it.

I'm a little confused by the latest rendering. I see what looks like a 3-pin fan header and another 3-pin header. There should be a 2- or 3-hole via for the trim pot, and a standard 2-pin header for a fan. Those more modern fan headers look quite out of place on a 386 based system. There wouldn't be anywhere for the tach wire to go.

EDIT:
Interestingly, this is what the fan headers used to look like on upgrades of this era: download/file.php?id=145118&mode=view
Notice how they used female machine pins?

The second header is your trim pot. It just shows up as a pin header in the 3d render. Don’t let it fool ya haha.

The rpm pin will go nowhere. Just has a spot for it to be soldered, with a two pin header installed it basically looks the same as you pictured. If you want, I could edit the silkscreen to not show the outline of the modern header?

Question, currently I am using .020” vias with .016” holes and .005” traces

but if .005” will work I suggest we leave trace at .005 as going larger will mess up the ground planes a lot. Will .005” traces work?

If these aren’t going to work for signals I need to know as changing them later will cause more work. I would have to go back and redo some work as it is if I change them. Making the traces .0075-.010” might be possible.

Looking at the adapters on 12,

The second one on the page looks like pin one of the small socket is left bottom while the large socket is right bottom does that sound right? Which is odd, kinda like they rotated the sockets 90 degrees apart? Is that the case? On this one I have the footprints are aligned with pin one on the same corner for both sockets. Relative to the small socket which is the one that matters it seems I have the vrm on the same side as it does.

The first adapter on page 12 looks like it has the mosfet stuff on the opposite side from mine

I'd personally ditch the tachometer header for the fan. Its presence increases the probability of someone using it incorrectly. I think the more retro look without the tach pin looks better. I'd label the 5V and the GND though.

I don't have adequate PCB design experience to comment on trace width. However, what I can do is look at various 386 and 486 interposers and make some general observations. 0.005" = 127 microns. For the 386/486 interposers in my possessions, the units which have 127 micron traces still are using larger trace widths for Vcc and GND. My caliper measures 220 microns for these larger traces, which I suspect is 0.01", or 254 microns. So if you are to copy what others have done, then you'd use 0.01" for Vcc/GND and 0.005" for the others.

However, I have two revisions of the same adapter, and on the other revision, they made all trace widths the larger variety, or 0.01".

Are you referring to photos 20201118_200431.jpg and 20201118_123708.jpg ? I'll copy them again with the underside rotated. In this image, I see PGA-168 pin 1 at the top left. For PGA-132, you need to mentally look at it from the top view, rather than the bottom view, and I see pin 1 on the bottom left. I suppose we'd want the orientation to be such that the average of all traces are the shortest length.

What size tantalum SMD caps are shown in your latest rendering?

Looking at Blavius' message about this jumper JP1, I do not follow what it does. He writes, "there is a solder jumper that allows to set pin J1 to 5V or vcc (3.5V). Only make this 5V for the SXL-G40 and SXL2-G50, all other SXL processors need vcc (3.5V)." But J1 is a header for MEMW#, GND, and 5V. He is changing the fan voltage to 3.5 volts using the lower jumper position and 5V with the upper? Fan should always be 5V. Maybe I have misinterpreted something here. Do you know what position does what? Maybe we should eliminate it?

Unless it's where you have room for it, I don't find it necessary to have the Cin capacitors for the VRM underneath the CPU, if it compromises room eg. for extra COut 😀 And I'd always prefer to have some 0603 100nF capacitors also 😀

Can you Draw a sketch of your suggested capacitor configuration?

Jumper:

I would have to look at the project file and see how it is wired, but I imagine one solder bridge jumps from 5v to vcc on the fet.

The fan can run from the vcc5 of the lower socket. Which will only go to the fet and the fan.

feipoa wrote on 2022-09-13, 08:34:

I'd personally ditch the tachometer header for the fan. Its presence increases the probability of someone using it incorrectly. […]
Show full quote

I'd personally ditch the tachometer header for the fan. Its presence increases the probability of someone using it incorrectly. I think the more retro look without the tach pin looks better. I'd label the 5V and the GND though.

I don't have adequate PCB design experience to comment on trace width. However, what I can do is look at various 386 and 486 interposers and make some general observations. 0.005" = 127 microns. For the 386/486 interposers in my possessions, the units which have 127 micron traces still are using larger trace widths for Vcc and GND. My caliper measures 220 microns for these larger traces, which I suspect is 0.01", or 254 microns. So if you are to copy what others have done, then you'd use 0.01" for Vcc/GND and 0.005" for the others.

However, I have two revisions of the same adapter, and on the other revision, they made all trace widths the larger variety, or 0.01".

Are you referring to photos 20201118_200431.jpg and 20201118_123708.jpg ? I'll copy them again with the underside rotated. In this image, I see PGA-168 pin 1 at the top left. For PGA-132, you need to mentally look at it from the top view, rather than the bottom view, and I see pin 1 on the bottom left. I suppose we'd want the orientation to be such that the average of all traces are the shortest length.

What size tantalum SMD caps are shown in your latest rendering?

Commercial_SXL2-66_Interposer.jpg

I’m not using traces for the power and ground those are being carried by flood planes. (This is better)

Okay, I’ll remove the modern fan header

They are the larger size tantalum you mentioned earlier. I haven’t made them smaller.

Sphere478 wrote on 2022-09-13, 12:35:

Okay, I’ll remove the modern fan header

big mistake

you're making it more work to use the type of fan that 95% of people will have lying around all to accommodate some silly aesthetic "it looks out of place" bullshit

Hi guys! Amazing work going on in here! Had some crazy time at home and at work and couldn't reply, so I have some catching up to do:

maxtherabbit wrote on 2022-09-12, 13:23:

Yes the 286 and 368 halve the incoming clock signal. This does not mean that the buses between the CPU and motherboard (FSB) actually transfer at the same speed as the clock pin. They are still only changing on every other clock pulse.

This is indeed what I found as well, at the socket CLK2=40MHz, and my processor reports 20MHz. So, in terms of signal integrity you could take the lower bus speed. To be safe, I went with the higher frequency. I supposed the highest we wanted to run this interpower at was 80MHz, so I tried to optimize for that. Which brings me to:

Sphere478 wrote on 2022-09-12, 07:49:

Btw, it seems like you may understand some of the jdec standards a little better than I and possibly how to do some signaling considerations/testings that I have some gaps in. Obviously I’m nowhere close to a final draft here but if you have any observations or suggestions lemme know.

That would be too much praise. I found a good article , and used the formulas from there.
JDEC apparently accepts a +/-2.5% skew on signals.
For 80MHz, the period is 12500 picoseconds. 2.5% is 312.5 ps. Using the formula in the article (312/(85*SQRT(2.92))), in that time the signal propagates 54mm.
This means the trace can be 54mm longer or shorter than the clock, and be within spec.
I my design I took the longest trace and the shortest trace, and made the CLK2 trace length exactly half of the difference. This way the skew is minimized as much as possible. As my longest trace was about 100mm, with the CLK2 at half that, its all within spec.

feipoa wrote on 2022-09-13, 08:45:

Looking at Blavius' message about this jumper JP1, I do not follow what it does. He writes, "there is a solder jumper that allows to set pin J1 to 5V or vcc (3.5V). Only make this 5V for the SXL-G40 and SXL2-G50, all other SXL processors need vcc (3.5V)." But J1 is a header for MEMW#, GND, and 5V. He is changing the fan voltage to 3.5 volts using the lower jumper position and 5V with the upper? Fan should always be 5V. Maybe I have misinterpreted something here. Do you know what position does what? Maybe we should eliminate it?

Sorry, this was a little confusing. JP1 refers to pin J1:

As you can see at the bottom, J1 needs to be 5V for the TI486SXL-G40, and 3.6V (VCC) for all other variants. JP1 is a solderjumper which allows you to hook J1 to 5V or VCC. It has nothing to do with the fan.

Sphere478 wrote on 2022-09-12, 07:49:

Taking a closer look at what you did here the power planes appear to be kinda messed up. The signal trace routing looks relatively tidy and straightforward though for a two layer layout, good job. It could probably have been improved using four layers. Not bad, power planes need some tweaking though a few sections don’t appear to be connected? 😀 not claiming to be an authority, just some stuff that pops out. Good job, I can tell you put some work into it 😀

Thank you, that's very kind! It was quite some work to manually route all of this. Not sure I would do that again now that I discovered the autorouter exists 😉.