A short question to those familiar with general design of PC chipsets and how DRAM works.

In general, EVEN parity is calculated as plain sum of all significant bits mod 2, so such function should return 0 from all-zeroes or all-ones. There is also ODD parity, complementing result to two, which is, effectively, just an inversion of the EVEN parity.
But which of those is generally used on real PC chipsets? e.g. what exactly will be written into 9th bit via PD line if, say other data are all-zeroes? Is thee any standard? Can that be different on different systems?

I'm currently analyzing fake parity chips, specifically VT531000 and BP41C1000D. Both chips works pretty similar: they have 8 data bits inputs, inputs for /WR, /CASP and in case of BP41C100D, /RAS lines, and parity In/Out, which is in case of VT531000 is a single bidirectional port. So, each time /WR is inactive (HIGH), fake chip detects parity type by comparing incoming 9th bit with internally calculated parity and, apparently, changing polarity of the output driver until, with next write operation, polarity is updated. Then, when /WR, /RAS and /CASP are low, these chips turn on their output drivers from Z state and output the parity bit with according polarity, emulating assumed value, which would be stored in the parity memory.
Since both of them are reconfigurable on fly, it seems that both polarities are expected, which seems strange.