As that is a PCI-to-ISA bridge, wouldn't it make sense that all it needs is a mapping of PCI vendor & device IDs to a name, and possibly mappings of PCI configuration space values to GUI settings? And no code?

superfury wrote on 2024-11-08, 02:04:

From what I can find, only a barebones INF file seems to exist, which is basically a dummy driver that doesn't load anything and just report it's there?

Does the driver for said device even exist in some form or another (like actual sys file for Windows 9x or 3.x)?

I think most of the work is being done by BIOS to configure the bridge as well as host ISA controller in southbridge (namely PC/PCI portion) to communicate with it.

From what I know about PCI-ISA bridge (W83628/W83629 for example), the BIOS would eventually configure the system to hide the PCI-ISA bridge behind the southbridge so only the host ISA controller would be visible to the system, and anything to the PCI-ISA bridge as well as stuffs behind it would be transparent.

As for a "driver", I think it would be mainly code to configure the registers on the bridge (before hiding) as well as configuring the southbridge for necessary parameters meant to handle the bridge. I don't think OS would have code to actually do the configuration since this is usually done very early -- in BIOS, or in an environment where you have full I/O access such as DOS.

LSS10999 wrote on 2024-11-08, 02:27:

I think most of the work is being done by BIOS to configure the bridge as well as host ISA controller in southbridge (namely PC/ […]
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superfury wrote on 2024-11-08, 02:04:

From what I can find, only a barebones INF file seems to exist, which is basically a dummy driver that doesn't load anything and just report it's there?

Does the driver for said device even exist in some form or another (like actual sys file for Windows 9x or 3.x)?

I think most of the work is being done by BIOS to configure the bridge as well as host ISA controller in southbridge (namely PC/PCI portion) to communicate with it.

From what I know about PCI-ISA bridge (W83628/W83629 for example), the BIOS would eventually configure the system to hide the PCI-ISA bridge behind the southbridge so only the host ISA controller would be visible to the system, and anything to the PCI-ISA bridge as well as stuffs behind it would be transparent.

As for a "driver", I think it would be mainly code to configure the registers on the bridge (before hiding) as well as configuring the southbridge for necessary parameters meant to handle the bridge. I don't think OS would have code to actually do the configuration since this is usually done very early -- in BIOS, or in an environment where you have full I/O access such as DOS.

But both can't configure the IT8888 chip, since it only has registers from 50h-7Fh, not the official 04-3Fh the PCI bridge documentation mentions? Or is the bridge having those registers undocumented (they exist, but aren't documented in the chip documentation)?

The chip documentation(https://theretroweb.com/chip/documentation/it … 4a102950850.pdf) only mentions up to 0Fh, with 0Fh being reserved.
Then only 2Ch-2Fh are documented.
All other official 00-3F fields are simply "Reserved" and not documented?
That's 10h-2Bh and 30h-3Fh being "Reserved"?

What are you hoping to configure?

Wpcredit is your best bet

superfury wrote on 2024-11-08, 10:56:

But both can't configure the IT8888 chip, since it only has registers from 50h-7Fh, not the official 04-3Fh the PCI bridge docum […]
Show full quote

But both can't configure the IT8888 chip, since it only has registers from 50h-7Fh, not the official 04-3Fh the PCI bridge documentation mentions? Or is the bridge having those registers undocumented (they exist, but aren't documented in the chip documentation)?

The chip documentation(https://theretroweb.com/chip/documentation/it … 4a102950850.pdf) only mentions up to 0Fh, with 0Fh being reserved.
Then only 2Ch-2Fh are documented.
All other official 00-3F fields are simply "Reserved" and not documented?
That's 10h-2Bh and 30h-3Fh being "Reserved"?

See section 7 of the datasheet you linked for all the PCI configuration registers the PCI-ISA bridge has.

If you can see your PCI-ISA bridge in your system topology then you should be able to modify registers that you're allowed to make changes.

Some southbridges (e.g. ICH5) have bits to hide the PCI-ISA bridge behind it so you may not be able to access it directly, however.

LSS10999 wrote on 2024-11-08, 12:34:

See section 7 of the datasheet you linked for all the PCI configuration registers the PCI-ISA bridge has. […]
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superfury wrote on 2024-11-08, 10:56:

But both can't configure the IT8888 chip, since it only has registers from 50h-7Fh, not the official 04-3Fh the PCI bridge docum […]
Show full quote

But both can't configure the IT8888 chip, since it only has registers from 50h-7Fh, not the official 04-3Fh the PCI bridge documentation mentions? Or is the bridge having those registers undocumented (they exist, but aren't documented in the chip documentation)?

The chip documentation(https://theretroweb.com/chip/documentation/it … 4a102950850.pdf) only mentions up to 0Fh, with 0Fh being reserved.
Then only 2Ch-2Fh are documented.
All other official 00-3F fields are simply "Reserved" and not documented?
That's 10h-2Bh and 30h-3Fh being "Reserved"?

See section 7 of the datasheet you linked for all the PCI configuration registers the PCI-ISA bridge has.

If you can see your PCI-ISA bridge in your system topology then you should be able to modify registers that you're allowed to make changes.

Some southbridges (e.g. ICH5) have bits to hide the PCI-ISA bridge behind it so you may not be able to access it directly, however.

What I mean is: does the IT8888 have BARs in the 10h-33h range? The documentation of the chip, much like the piix southbridge doesn't mention them, other than 'reserved'?
Or do they follow official specs with 1 memory BAR at 10h-13h for it's 16MB aperture and bit 1 of the command register to enable it (and put it at 0MB if it's disabled (bit 1 cleared in the command register) for compatibility with legacy ISA)?

superfury wrote on 2024-11-08, 12:57:

What I mean is: does the IT8888 have BARs in the 10h-33h range? The documentation of the chip, much like the piix southbridge doesn't mention them, other than 'reserved'?
Or do they follow official specs with 1 memory BAR at 10h-13h for it's 16MB aperture and bit 1 of the command register to enable it (and put it at 0MB if it's disabled (bit 1 cleared in the command register) for compatibility with legacy ISA)?

I just read from here, though I still have a lot to learn to understand the details.

You can always use tools that can access PCI configuration registers to read from those reserved locations and see if they contain the values you're expecting.

Maybe some datasheets simply don't document standardized registers unless they have something that would violate the standard, or things that system/BIOS designers need to pay explicit attention to.

For now, I've implemented the upper registers as documented. But the lower registers has 1 BAR implemented (for the BIOS specifying a memory area to use with the address registers, with a size of 16MB).

I've also made the command register bits 0-2 writable, so that the BIOS can detect and enable the software's use of the BAR for detecting if it's actually filled.

Software that needs a memory area to use for (in this case a Tseng VGA card using 16MB ISA space mapped anywhere in memory) mapping the 16MB memory hole into a different memory location can simply use that field to fill the actual memory BARs at location 70h-7Fh if it wants to remap it to a safe memory address location without conflicts.

In the case of the i440fx BIOS I'm using (with 128MB of RAM) the BIOS sets up the location to E7000000, so that's a safe place to place things like the Tseng framebuffer using the remapping functionality of the card (using registers 3CD for read/write location on AX (1MB location, so that's specifying bits 20-23), register 30h bits 0-1 on W32i (4MB location, so that's specifying address bits 22-23 in that case)).

Although the register 3CD mapping for the ET4000AX isn't documented by the chipset itself, but it must be, due to it being the only 'unused' register in linear mode.

One interesting thing about the bridge is that the header type register specifies it as a type 0 (as documented). So that'd be dword bars from 10h-27h, card bus at 28-2Bh, expansion ROM address at 30-33h, interrupt nr at 3Ch, and interrupt pin at 3Dh, with min grant at 3E and max latency at 3F.

I don't kniw what BARs are present on the chip, though, as I can't find any documentation on it.
For now only 1 BAR and modified the command register bit 1 to be r/w instead of r/o set (as documented).
The BIOS setups the BAR to 7E000000h. And the command register bit 1 set (enabling it).
Though that makes no sense for an ISA address space, as it needs to be at 0h by default?
It also doesn't touch registers 40h+?