According to the documentation I can find, they al say that the focus processor (if there is one) is the processor that has a pending request or is servicing it.

What is the purpose of this? If it has a pending request (the IRR bit is set), it can't handle said interrupt?
And if it's servicing it, it may be able to handle it later, assuming the IRR bit isn't set?

Or is the interrupt simply delayed from being received, causing retries on the bus until it can actually receive it?