How are the cache bits in the x86 paging layers (PDPTE, PDE, PTE) combined with the CR3 register bits and CR0 register bits?

From what I've gathered so far:
- Page Cache Disable of the CR0 register is pretty much OR'ed with just the current level of lookup (see below on the used second source for the 'current level').
- Page Write-Through uses the flipped Not-Write through bit of the CR0 register AND'ed with the current level of lookup (see below on the used second source for the 'current level')

The second source being:
- PDPTE lookups (when loading CR3 or enabling PAE) use the CD0 register directly (effectively the second source is the CR0 register itself)
- PDE lookups uses either PDPTE bits(PAE) or CR3 bits(non-PAE)
- PTE lookups use the PDE bits.

Is that correct behaviour?