So far I've been implementing the W32P documentation bits inside the W32i emulation I've built.

But the ACL Suspend/Terminate register has some weird bits.
Bit 3(host write enable) and 2 (host read enable) both say they restore queued data (bit 3) or extract queued data (bit 2).
But reading the queued registers already reads the queued registers, as with the W32i? So what is meant by 'queued data'?

The ACL status register reports bit 4 as ASUS: Acellerator Suspended Status. Apparently it's set when the accelerator is suspended (by bit 0 of the suspend/terminate register). But when is said bit cleared?