Are all TR register references (stack switches to a higher privilege level(ss[n]:esp[n] loading), Interrupt redirection bitmap (using the IOPB bitmap pointer as well), IOPB bitmap and it's pointer, as well as just hardware (x86) task switching (loading and saving the state into the TSS)) performed like from privilege level 0(kernel mode) no matter what the current CPL is (the same for x64 interrupt stack table entries, but that's outside of this scope)?