DrSwizz wrote:
Thank you for the article; I have saved it in my personal archives. I had no idea about non-SRAM-based cache for socket 7 boards. Mcache appears to be fast DRAM (7.5 ns for these chips), with performance allegedly equivalent to pipeline-burst SRAM. Apparently, benchmarks cannot detect the difference between the two. The advantage of Mcache is for cost and size reduction. It looks like chipset makers had to build-in a specific refresh function for this new DRAM caching scheme. The reported half percent performance hit from needing to refresh the cache may be idealised?
Efforts to save cost, while not increasing performance, aren't terribly enticing from a retro computing stand-point.
I wonder if the presence of Mcache in one of my 430TX boards is the cause for the need to bypass DMI/PnP related detection in Speedsys (run speedsys.exe /sp)? I cannot run speedsys without the /sp command.
Plan your life wisely, you'll be dead before you know it.