amijim wrote on 2024-11-17, 16:08:
Hello there , as we know the Intel 430tx features an 64kb tag ram and can cache 64mb ram.What will happen if I install an 128kb or 256 tag ram? Will the mobo cache 256mb ram? I am about to find but has anyone tried it?
This won't work, because the chipset is designed in a way that it can not cache more than 64M of RAM. For 256K of cache, the limit is explainable by math: We are dealing with one of the simplest forms of implementing an associative cache (you might call it a degenerate case). An associative cache associates a certain memory address with one or multiple locations in the cache that might contain the value at that memory address. The 430TX uses (as most 386, 486 and Socket 7 chipsets do) "direct mapped" cache, which means there is always exactly one location in cache that can be used for a certain location in memory. The implementation in most of the chipsets work like this: You split the memory into pieces, each being as big as the L2 cache. The position in cache that may be used to store a value from memory is the position of that value inside the piece. Let's look at an example:
The cache size is 256K, so the memory is split into pieces of 256K each, one ranging from 0..255K, the second one ranging from 256K..511K, the third one ranging from 512K to 768K (let's not worry about what's up with the addresses between 640K and 1M, which is an entirely different can of worms). So the value at address 1024 (1K) in the cache may be from the first piece, in which case it would be the value that's in memory at address 1024. It could also be from the second piece, in which it would be the value stored at 257K, or from the third piece, which would be the value stored at 513K. When the chipset needs to determine whether a specific address of main memory has a copy in cache, it needs a way to find out the number of the memory piece that is cached at that cache location. In the previous example, if the processor requests the memory at address 513K, the chipset is going to find that this memory location may be backed by address 1K in cache, in case the cache at address 1K is currently caching data from the third piece of memory. So the chipset needs to look up which piece of memory is currently associated with the cache location at address 1K. If it happens to be the 3rd piece (typically indicated by the number 2, because computers like to start counting at 0), the cache contains the required data, and the chipset doesn't have to access the main memory. The memory that is used to contain the piece number is the tag RAM this thread talks about. The 430TX chipset interfaces to the tag RAM using 8 data lines, which allows 2 to the power of 8 = 256 different pieces of memory, each 256KB to be identified as "being currently in the cache". 256 pieces of 256K each make up for 64M.
In the case of 512KB of cache, an 8 bit wide tag RAM could be used to support 256 pieces of 512K each, which would be 128MB of cacheable memory. Alas, the Intel 430TX chipset does not support this mode of operation. Super Socket 7 chipsets by other vendors like ALi or VIA do, though. Even at 512K of cache, the 430TX only allows the first 64M to be cached, effectively only making use of 7 tag bits.
So, now we can also take a look at how big the tag RAM had to be. So, basically for every "cache location", the chipset needs to look up what piece of main memory is currently backed by this cache location, but I did not yet define the size of a "cache location". These cache locations are called "cache lines", and due to the way the L1 cache and the front-side bus of socket 7 processors is specified, a cache line size of 32 bytes makes most sense. This means that every block of 32 bytes in the cache is associated with the same piece of main memory. For 256KB of cache and a cache line size of 32 bytes yields a total count of 8192 cache lines. This means the tag RAM has to store 8192 entries of 8 bits each, which is 64 kilobits (like what you are referring to in your question). If you have 512KB of cache, there were 16K (16384) cache lines, and you need a tag RAM of 16K entries x 8 bits = 128 kilobits. A tag RAM with more entries just allows managing a bigger cache. It does not allow managing more RAM. To manage more RAM, you need more data bits at once. The chipset has no time to look at multiple locations in the tag RAM to combine the bits for more than 8 tag bits.
There are 430HX bits that support eleven instead of 8 tag bits, increasing the cacheable area from 64MB to 512MB. Typically, boards that did support this (only a few consumer boards did) just used two 8-bit cache chips and left 5 bits of the second chip unused, because 8-bit chips were the most common chips at that time. It's a unique property of the 430HX chipset that it allows 11 tag bits to be connected to it. The 430TX chipset has just 8 pins to connect to the data of the tag RAM, and even the 430HX uses 11 pins only in a special configuration, and many boards do not connect anything to the extra pins (balls to be exact).