I am using my PC Chips M912 for testing. The manual doesn't even list a Cyrix or AMD 5x86 and the latest CPU listed in the manual appears to be the Intel DX4. When I put in the Cyrix 5x86-100 and use the i486DX4's jumpers, everything seems to work just fine. The BIOS has an option to set the cache in write-back or write-through mode, however both settings yield the same benchmark results. CHKCPU says the L1 cache is in write-back mode for both settings.

I can use Evergreen's software, ET586.exe /WBD, to set the L1 cache back into write-through mode, which seems to work. Unfortunately, the benchmark results are still the same as before. I'm not really sure what to make of all this. Either the CPU is stuck in write-back mode, or write-through mode, but I don't know which. If I use ET586 to set the L1 cache into write-through mode, then use /WBE to set write-back mode again, the system will hang when I try to run a program.

Using the Evergreen interposer did not change the benchmark results. The only thing it did allow me to do was to allow the CPU to run in write-back mode again after first having set it to write-through mode.

I'm guessing that this motherboard might not be the best candidate for this experiment. Perhaps using a 386 motherboard with the Transcomputer module + Evergreen module is a better bet to ensure there is no L1 write-back support.

Nobody has heard about Evergreen's "cache-back" technology then? A fellow forum member brought it up to me a few months ago and I have encountered it in a few magazine advertisements, however I am starting to wonder if there is any technology there. They tend to put the trademark after cache-back, that is, "cache-back(tm)". Perhaps it was just a gimmic - enable write-back cache via CPU registers and hope it work, similiar to how the BIOS would write to the CPU registers.

So it looks like the CBE part of ET586 /CBE is only for the OS/2 operating system. In DOS, there is only the a write-back enable or disable feature, while OS/2 has write-back enable/disable and cache-back enable/disable.

Never heard of this - do you think people even bought such a thing?
Maybe this was some kind of scrap product that emerged as a result of other, more vital, ones...

I don't know. I suspect it is mostly a marketing gimmick. I need a more suitable motherboard to test this feature out on.

I think this is mainly to eliminate combatiblity problems with some CPU's on older Mainboards ?

Yeah, presumably that is what the Lattic chip on the interposer does.

Evergreen charged an extra $20-$30 for the cacheback feature. The upgrades that didn't support cacheback didn't come with the lattice IC, so obviously it contains some magic.

Interesting. Could you point to the source of that information?

I know this through a combination of posts on usenet, and these photos. No CB jumper, no lattice IC.

Oh nice find.

Do you have any idea what the BLK/RED holes are for?

And what about this CB jumper? I assume CB is for write-back cache. Move the jumper up two pins, it is for write-through cache. What about no jumper, or jumper on the middle?

Lastly, there is this OD jumper, which I assume is intended for an overdrive socket. There are 3 possible positions: 1-2, 2-3, no jumper. Any idea what this jumper does? I wonder if one such position is to bypass the onboard VRM?

Have you seen a manual for this interposer? I could only find the manual for the Evergreen manual with the QFP Am5x86 soldered on.

So you would need to find one of these lattice chips, pray to the electronics gods that it can be poked hard enough to reveal its workings, or just use enough knowledge to do it yourself from scratch.

My limited experience with these things in macintosh products tells me the lattice chip is just watching the data bus for a certain combination of 1's & 0's and intercepting certain register commands to replace them with something else. The lattice chip is just a basic CPLD by the looks of it.

it might be as simple as the program sending a special set of data through the processor that the cpld will trigger, and send the corrected data to the cpu that causes the missing functionality to work. I'd wager getting the chip would be fall down easy, but finding the program and programmer would prove to be challenging.

I'd wager the black/red are for the black & red leads of a small 5v fan.

I would guess that the cache jumper lets you set WT, WB and CB. I will let you know when I take possession of my Evergreen kit. I'll scan the manual and upload it to VOGONS.

is it possible to read these cpld chips after the fact?

Only if protection bit isn't set, which it normally is. If there's no storage in the chip you can brute force the logic out of it by inputting all possible combinations and observing the output.

So if the "protection bit" isn't set, you can read these logic controllers like an EEPROM, that is, copy it and write it to another logic controller?