AMD did not only legally forced to do not use Intel P6 front side bus (AGTL), they also wants to make CPUs faster than Pentium-II. To make this thing real they had licensed a DEC EV6 bus used in Alpha CPUs. It was faster than Intel AGTL and allowed transactions with double data rate, which makes AMD processors with DDR RAM faster than Intel with DDR (or Rambus). Intel maked similar FSB only for Willamette core, and only then got memory bandwidth similar to AMD Athlon's.

Ultimately it all comes down to cost. The slot and the socket might cost about the same but once you can die shrink the CPU and integrate the cache it suddenly becomes a lot simpler and cheaper.

640K!enough wrote:

That approach would quickly become unmanageable in a slot design, unless they moved to some sort of multi-row, high-density pin header. With their multi-processor and multi-core designs, more pins are inevitably required.

I don't think so, because the FSB protocol allows for multiple CPUs to be connected to a single socket/chipset. That is exactly how they implemented the Pentium D: two Pentium 4 dies connected via their FSBs.
That might also have worked on a Slot 1 approach.

When I read this thread title I picture my Thermalright Ultra-120 Extreme tower cooler mounted to the side of a Slot 1 CPU...

RaverX wrote:

If Intel decided to keep the slot format for the CPUs it coudl do a lot of intersting things. Imagine that instead going P4 route they would keep the PII architecture, clocked a little highe, with cache on the CPUr, but with extra slower (but a massive amount) cache memory. Then maybe 2 or even 4 CPU on the PCB, with a huge amount of shared L3 cache... But they went Netburst 🙁

Eh, the slot design has became completely redundant as transistor density has increased over the years. Intel can basically put as much cache and execution units onto a CPU as it sees fit. It now chooses cache size and configuration based mostly on performance vs power usage vs die area concerns. If adding another 20meg cache would greatly improve the general use case CPU performance, they would do so without a second thought.

There is nothing about a slot that would improve CPU compatibility vs plain old sockets. The compatibility of CPUs and motherboards is on whole a design choice, one that I generally don't see as bad one. Pairing motherboards and CPUs that are years apart tends to create a mismatch of features and performance, and given that a new motherboard can be made pretty cheap and still perform very well, maintaining compatibility to put vastly newer CPUs on old motherboards is a waste of effort and leaves performance on the table.

Ah, one of my favorite eras in x86 computing.

One small correction on some earlier posts, the first Slot 1 CPUs had four cache chips, not two, plus the tagRAM chip.

Pentium II Klamath CPU's looked like this, with the four 128K cache chips. These were only in the SECC package.

The Pentium II Deschutes CPU reduced the cache chip count down to two 256K chips. These were in SECC and SECC 2 package.

Then starting with the PII 450, and later revisions of the PII 400 and 350, we got an OLGA core and a re-arrangement of the cache chips. This same layout was also used for the PIII 450-600 Katmai CPUs. These were in SECC (only PII) and SECC 2 (PII and PIII).

Then finally with the Coppermine core, Intel put the L2 cache on the CPU die, eliminating the need for cache chips, and leaving the Slot 1 PCB very empty. These were only in SECC 2 package.

As others have said, the Slot 1 design was a cost/performance compromise between the cheap/slow motherboard L2 cache of the Pentium and the expensive/fast full-speed L2 cache of the Pentium Pro. Over the course of 1997-1999 Intel made the move from 0.35 µm to 0.25 µm, and then 0.18 µm process technology, and as a result was able to integrate a large enough L2 cache on the CPU die at a reasonable enough cost to sell to consumers. It was also a way to force AMD off intel platforms. Once both of these objectives had been achieved, intel no longer needed the Slot 1 platform, and moved back to sockets. The Slot 1 design was a result of the state of semiconductor process technology and the positions of the key players of the industry in the mid to late-1990's.

The Celeron got on-die L2 cache even earlier than the Pentium III in the form of the famous Celeron 300A with Mendocino core. This was mostly a result of negative press on the original cache-less Celeron 266/300.

Katmai500 wrote:

As others have said, the Slot 1 design was a cost/performance compromise between the cheap/slow motherboard L2 cache of the Pentium and the expensive/fast full-speed L2 cache of the Pentium Pro.

To some extent, but that justification breaks down when you look at the fact that Motorola/IBM accomplished the same thing on a smaller board, and using a ZIF socket. They didn't have to design that big monstrosity, they chose to do it, unless what we're saying is that the P6 core was so thermally-inefficient, by comparison, that the metal plate was essential.

Don't misunderstand, though, I also like hardware of that era, and your summary of the different generations of Slot 1 processors was interesting.

Agreed. Intel even did a much smaller package with the mobile Pentium II in MCA package which launched in early 1998. Though by that time they were on the 0.25 um process and using the 256K cache chips rather than the 4x 128K in the early Pentium II's from 1997.

My guess is the second motive: excluding AMD from their platform, had a lot to due with the design. Perhaps making the platform appear drastically different from the previous sockets might have made any litigation from AMD easier to fight?