It's chipset (memory controller) dependent, sometimes differing per revision (ALi Aladdin V...)
If you don't want to get bogged-down in specifics, just look it up for every chipset you want to use.
But in terms of concepts... see cache as something faster that inserts itself between CPU and memory. The CPU can address a lot of memory (pretty much every CPU with cache can do at least 4GB), but memory and cache controllers can't handle that much. Your max memory is determined by the memory controller, max cache is determined by the cache controller. If your cache controller can't address as much as the memory controller, you potentially end up with memory that can be addressed by CPU and memory controller but not by the cache controller. That means that every single read from CPU to that memory goes all the way to (slow) system memory, and is not covered by the (fast) cache memory. If the CPU wants to read from an address that is cached, the cache controller reads it from the cache so the CPU gets it much faster.
In general memory and cache controller could both handle more than anything realistic at time of release of a platform. You only get into problems when adding (far) more memory to a system than would have been realistic at release.
Consider that the i430FX chipset was released in 1995. 8MB of RAM cost upwards of EUR 250 (not corrected for inflation..>). The chipset could cache 64MB. That would have cost EUR 4000, just for the RAM. Realistically this was not a limit at the time. If you were throwing that sort of money at a system you wouldn't have been buying a consumer-grade i430FX system but some or other workstation. These days 32MB SIMMs are dirt cheap, so you could easily equip a board with the 128MB the memory controller could address. Then you hit the cacheable limit and half your memory is not cached by L2 cache. Not good. But if you want 128MB RAM you're basically using the wrong platform... the only case where you might have realistically have hit those limits would be with Intel i430TX and ALi Aladdin V chipsets with the same limits in 1998-1999, although in the case of the Aladdin V it was a bug fixed in later revisions (rev. G), as by 1999 128MB RAM wasn't crazy.