quick google translate of this note
https://tnt23.livejournal.com/881036.html

Chips/chipsets in Creative PCI cards
Live!- EMU10K1, codename Alice
The chip is fixed at 48 kHz

APS - EMU10K1 + Xilinx
The chips are fixed at 48 kHz, Xilinx is responsible for routing

Audigy - EMU10K2 CA0100, codename Alice2 The chip is fixed at 48 kHz, differs from 10K1 only in increased E-MU power
1010V1/0404V1 (used in 1820, 1820M and the first version of 1212M) - EMU10K2 CA0100 + Xilinx Spartan IIE XC2S50E
Xilinx is responsible for signal routing and PLL (clock generator frequency conversion)
signal recalculation, without effects cards support frequencies up to 192 kHz
Codenames: 1010V1 - Hana, 0404V2 - Hana Lite

Audigy2/2ZS/4Pro - EMU10K2 CA0102/CA10200 + P16V CA0151, codename (of the whole bunch) Alice 3
EMU10K2 is fixed at 48 kHz, it differs from the old version (CA0100) by the ability to work in tandem with P16V
CA10200 - just the name CA0102 according to the new classification, sticker with this number glued to the Audigy 4 Pro chip over the inscription CA0102
P16V allows you to output sounds with a sampling rate of 48/96/192 kHz without effects and processing.
The cards themselves have code names that differ from the code name of the chip: Audigy2 - Apollo, Audigy 2ZS / 4Pro - Atlantis

Audigy2ZS (PCMCIA) / Audigy2 Value / Audigy4 - EMU10K2.5 CA0108 / CA10300, codename Tina
CA0108 and CA10300 do not differ from each other and are interchangeable (CA0108 is usually found on A2V, CA10300 on A4, but there are exceptions)
The newer CA0108/CA10300 differs from CA0102/CA10200 by the integrated P17V chip and lack of FireWire.
P17V differs from P16V by supporting 44.1 kHz without signal recalculation.
The card for notebooks (A2ZS PCMCIA) is codenamed Tina2, despite the same chip

E-MU 0404V2/ 1010V2 / 02Сardbus (02Cardbus is used in 1616, 1616M, and 1010V2 is also used in the second version of 1212M) - EMU10K2.5 CA10300 + Xilinx Spartan 3E XC3S100E Xilinx is responsible
for signal routing and PLL, thanks to PLL CA10300 supports 44.1 kHz without signal conversion
Integrated in CA0103 block P17V not used
Code names: 1010V1 - Haole, 0404V2 - Haole Lite, 02Cardbus - Mana

X-Fi (all PCI except XtremeAudio, Hendrix, Elite Pro and Prelude) - CA20K1 + P16V CA0151
CA20K1 (codename Zenith) differs from EMU10Kx in its redesigned architecture and increased power The
built-in PLL in CA20K1 and support for striping (separation>processing>connection) of samples allow the chip to process any frequencies without oversampling
P16V (supporting any frequencies this time due to the built-in PLL in CA20K1 ) is used to route signals to the front panel and

X-Fi Elite Pro/Prelude remote unit - CA20K1 + Xilinx XC9536XL
Xilinx is responsible for X-Fi signal routing Hendrix - CA20K1 + CA0112
CA0112 (codename Golden Gate) differs from CA0151 in UAA support (allows the card work without drivers with basic audio output capabilities)

X-Fi Titanium - CA20K2
The CA20K2 differs from the CA20K1 by supporting the PCI-Express bus, on-board DDR memory instead of SDR, and the integrated CA0112

Live! 24bit/AudigyLS/SE/Value/X-Fi XtremeAudio - CA0106/CA0111, codename P17
independent version of P17V with the implementation of all algorithms by drivers on the computer's CPU
CA0111 differs from CA0106 only in the technical process and are interchangeable

X-Fi XtremeAudio PCI-Express/X-Fi [ XtremeAudio] Notebook - CA0110, codename Tina3
CA0110 differs from CA0110 in support of PCI-Express and UAA bus

Brief specifications and descriptions of the chips:

EMU10K1
Process technology - 0.35 µm
Core supply voltage - 3.3 V
Clock frequency - 100 MHz
Number of transistors - 2.44 M
Power of the entire chip - 335 MIPS
Data format - 32 bit integer
DSP power - 50 MIPS
Number of SRC interpolators - 64
Number of channels from SRC to DSP - 16
Maximum number of simultaneous accesses to stored delay values ​​- 128 internal + 32 external

Fixed linear pipeline architecture: SRC and MIDI synthesis block > effect processor (DSP)
All filtering (necessary for EQ and 3D positioning) and mixing is done by the DSP The DSP
instruction set includes 16 operations, almost all operate on 3 operands (add 3 digits or add the first to the product of the second)
DSP is synchronized with a frequency and performs 512 operations per sample
DSP power is stated based on a frequency calculation of 48 kHz * 512 operations * 2 (due to the ability to add 3 numbers in one operation, i.e. carry out 2 additions) The DSP has a built-in
delay storage unit (used for reverb and 3D positioning) with internal memory 8 KB and access to RAM via PCI

EMU10K2/2.5
Process technology - 0.18 µm
Core supply voltage - 1.8 V
Clock frequency - 200 MHz
Number of transistors - 4.6 M
Power of the entire chip - 424 MIPS
Data format - 32 bit integer
DSP power - 100 MIPS
Number SRC interpolators - 64
Number of channels from SRC to DSP - 64
Maximum number of simultaneous accesses to stored delay values ​​- 128 internal + 32 external

The chip architecture has not changed, almost all differences are quantitative:
DSP executes up to 1024 instructions for each sampling period
Internal delay memory increased to 16 KB
Bottleneck eliminated - the number of channels from SRC to DSP expanded to 64 SRC CA20Kx
work quality slightly improved Process technology - 0.13 µm Voltage core power supply - 1.2 V Clock frequency - 400 MHz Number of transistors - 51.1 M Power of the entire chip - 10340 MIPS/MFLOPS Data format - 32 bit integer/floating point DSP power - 1180 MIPS/MFLOPS Number of internal bus channels - 4096 Interpolation unit power - 7310 MIPS/MFLOPS Number of SRC/Change/Speed ​​interpolators - 256
Filtering unit power - 200 MIPS/MFLOPS
Number of simultaneously applied filters - 512 2nd-order IIR
Mixing/internal bus control unit power - 1210 MIPS/MFLOPS
Number of adders in the mixer - 256 Delay calculation unit power - 440
MIPS/MFLOPS
one sample period - 1024

Completely new architecture: the mixer manages an internal bus that links bidirectional channels all DSP function blocks
can access other blocks to perform delay calculations, filtering and tone / speed changes on them instead of consuming its own resources
DSP is not tied to the sample rate , has 4 independent subprocessors, each is 2xSIMD
The DSP instruction set includes 235 operations, many allow you to perform different operations in different halves of SIMD or operations on complex numbers The
chip has a built-in memory controller and all cards are equipped with 2, 24 or 64 MB, the memory is used for caching sounds and a block for calculating delays The quality of
SRC is radical improved