rasz_pl wrote on 2023-08-05, 06:51:

why CY7C1009D and not something like https://eu.mouser.com/ProductDetail/Alliance- … 8C401801-QC166N? 3.3V might be a problem, but Iv seen people use 3.3v sram in Amigas with success (>year with no failures)

Going 3.3V can be a solution. At my standard hobbyist's electronics retailer, I can get new CY7C1019DV33-10V (128k x 8, 10ns, 3.3V) for 2.65€ a piece. Dropping the operating voltage from 5V to 3.6V or something like that is not a problem at all. The issue I currently see is that these chips are not specified to be 5V tolerant, so they start clamping the data signals to 4.0V through their ESD diodes when you power them with 3.6V. If there are only TTL-type outputs on the local bus, this is likely not a problem, because they can't drive "high" very hard. On the other hand, if there are 5V CMOS outputs, this clamping action can cause excessive current on the data lines. Do you have any pointers to discussions of the Amiga people using 3.3V SRAM at 5V, so I can check their experience?

The memory chip you suggest will not work. That's not asynchronous SRAM as required by 486 processors, but around 2 generations newer. They can be seen as the successor of pipelined burst SRAM. Their bus protocol is completely clock synchronous like the interface of SDRAM. They provide really high performance for systems that can use them, but a 486 mainboard just doesn't match synchronous ZBT SRAMs.

https://hackaday.com/2021/01/08/the-amiga-100 … comment-6309849
Afaik nobodys extension died in 2 years since https://www.amigalove.com/viewtopic.php?t=1689&start=50
is there anything driving the bus above 3V on 486 board? ram probably wouldnt, 3v cpu wouldnt, chipset?
sync/async is indeed no good 😀 I just sorted by price and speed. Still at 3.2ns there is plenty of time for fpga in between is someone decided to go that route.
So maybe ISSI IS61WV25616EDBLL-8TLI-TR, 8ns and 256 k x 16 to simplify board layout, max 4V + 0.5 so not that bad. 10ns version available at jlc https://jlcpcb.com/partdetail/948329-IS61WV25 … LL10TLI/C883296 to enable ordering already assembled board.

rasz_pl wrote on 2023-08-05, 09:35:

So maybe ISSI IS61WV25616EDBLL-8TLI-TR, 8ns and 256 k x 16 to simplify board layout, max 4V + 0.5 so not that bad.

I've already seen those x16 chips. using the full x16 bus width when substituting SRAM on 486 mainboards requires external logic. You need bytewise write enable, but reads must be unconditionally enabled for all bytes. These x16 chips do have byte enables, but they affect both the read and the write operation, and thus are incompatible with the interface between the cache controller and the cache chips. Of course, when you design your own cache controller, you will have no issues generating the signals to drive a x16 or x32 asynchronous SRAM (the 486 uses byte enable signals for both reads and writes on the FSB, so the signals are already there), but in this case I want to just emulate 32k x 8 / 64k x 8 / 128k x 8 asynchronous SRAM.

rasz_pl wrote on 2023-08-05, 09:35:

https://hackaday.com/2021/01/08/the-amiga-100 … comment-6309849

So they are using AS6C6416 chips on the Amiga 5V bus. The experience is likely transferrable to other 3.3V chips by Alliance of the same generation at least. Thanks for the link.

rasz_pl wrote on 2023-08-05, 09:35:

is there anything driving the bus above 3V on 486 board? ram probably wouldnt, 3v cpu wouldnt, chipset?

IIRC the scope traces showed that the chipset and the SRAMs at least are clearly driving to 5V (but they obviously don't show how hard it is driven). Normal PS/2 SIMMs also drive to 5V, but some of the latest PS/2 SIMMs use 5V-tolerant 3.3V RAM and dropper diodes (Z-Diodes?). Those SIMMs will not drive to 5V. Indeed, a 486 CPU will not drive 5V, but if you toast your AMD 5x86 at 4V to get 180MHz, you might get above the recommended operating condition of Vcc+0.3V with a Vcc of 3.3V. Likely, a 3.3V CPU is no practival issue with the 3.3V cache RAMs powered at 3.5V.

rasz_pl wrote on 2023-08-05, 09:35:

sync/async is indeed no good 😀 I just sorted by price and speed. Still at 3.2ns there is plenty of time for fpga in between is someone decided to go that route.

Using the sync burst option of these chips can be challenging because you need to set up linear burst / interleaved burst on them. This is a software-configurable option on latest-day 486 chipsets, but that won't reach to the cache module. So maybe a FPGA-based burst SRAM adapter needs to have a "Cyrix 5x86/ other" jumper? Cyrix 5x86 processors use signalling that is compatible with either linear or interleaved burst until you set the "linear burst enable" bit, so they can be booted with cache expecting linear burst even if the chipset assumes the processor is using interleaved burst.

Or you don't burst on the cache side at all, if the synchronous cache chips are fast enough to do non-burst access into a 60/66MHz 486 bus in a X-1-1-1 burst.

rasz_pl wrote on 2023-08-05, 09:35:

is there anything driving the bus above 3V on 486 board?

I just scoped the stuff:

• Address lines: (without active PCI bus masters): low: 0V, high: 3.6V (VCore is 3.6 or 3.7 at the moment).
• Data lines: Mixed high levels between 3.6V and 5V or somewhere in-between
• Control lines: /WE, /OE, /CE and the one address bit driven by the chipset: 5V

So it looks like there are CMOS-type drivers in the CPU (at Vcore) and the chipset (at 5V), and possible TTL drivers at other places. The RAM stick I currently have in that board uses 3.3V RAM with 2 diodes in series to drop the 5V operating voltage, so "in-between" level is likely originating in the RAM.

I do see overshoot to slightly above 5V on the address lines (measured near the cache chips). As I don't see the same amount of undershoot, it looks like the cache clamping over/undershoot to GND-0.3 to Vcc+0.3 or something like that. Overshoot spikes to 5V probably don't indicate any compatiblity issue with 3.3V RAM chips.

mkarcher wrote on 2023-03-13, 20:40:

mockingbird wrote on 2023-03-13, 00:07:

Fascinating tests... So far I am finding PCI 8881E/8886B (HOT-433) a lot more stable than the VLB VL/I-486SV2GX4...

That's comparing apples and oranges. The 8881E and 8886B are the last revision of the UMC 8881/8886 chipset, which is likely years newer than the SiS 471 on the VL/I-486SV2GX4. The SiS competitor to the UMC8881/8886 is the SiS 496/497. Again, the only latest revision of that chipset has EDO support. You can get VL-capable boards with both the SiS 496/497 (like the Lucky Star LS486E, the Soyo 4SA(W)2, the Asus PVI-486SP3) and the UMC8881/8886 (like the Gigabyte GA-486IM).

Would there be any reason to expect the SiS 496 to have much different performance in a cacheless+EDO DRAM configuration than the UM8881?

jakethompson1 wrote on 2024-02-21, 18:04:

Would there be any reason to expect the SiS 496 to have much different performance in a cacheless+EDO DRAM configuration than the UM8881?

I don't think so. I expect both chipsets to implement the same "industry standard" patterns to access EDO RAM. This also means you likely can use the publicly available datasheet for the SiS496 to get an idea how the UMC8881 accesses EDO RAM.

mkarcher wrote on 2024-02-21, 18:57:

jakethompson1 wrote on 2024-02-21, 18:04:

Would there be any reason to expect the SiS 496 to have much different performance in a cacheless+EDO DRAM configuration than the UM8881?

I don't think so. I expect both chipsets to implement the same "industry standard" patterns to access EDO RAM. This also means you likely can use the publicly available datasheet for the SiS496 to get an idea how the UMC8881 accesses EDO RAM.

Can we summarize the whole thread as: if you don't overclock, at 33 MHz the EDO RAM is capable of 2-1-1-1 but the DRAM controller isn't, so it is underutilized and you still need external cache to bridge the gap?

jakethompson1 wrote on 2024-02-21, 19:02:

Can we summarize the whole thread as: if you don't overclock, at 33 MHz the EDO RAM is capable of 2-1-1-1 but the DRAM controller isn't, so it is underutilized and you still need external cache to bridge the gap?

That is, essentially, the same problem early Pentium chipsets had: Re: IWILL P54TS Turbo switch

Unfortunately, we can't plug Pipeline Burst cache into 486. Yet.