rasz_pl wrote on 2023-08-05, 06:51:

why CY7C1009D and not something like https://eu.mouser.com/ProductDetail/Alliance- … 8C401801-QC166N? 3.3V might be a problem, but Iv seen people use 3.3v sram in Amigas with success (>year with no failures)

Going 3.3V can be a solution. At my standard hobbyist's electronics retailer, I can get new CY7C1019DV33-10V (128k x 8, 10ns, 3.3V) for 2.65€ a piece. Dropping the operating voltage from 5V to 3.6V or something like that is not a problem at all. The issue I currently see is that these chips are not specified to be 5V tolerant, so they start clamping the data signals to 4.0V through their ESD diodes when you power them with 3.6V. If there are only TTL-type outputs on the local bus, this is likely not a problem, because they can't drive "high" very hard. On the other hand, if there are 5V CMOS outputs, this clamping action can cause excessive current on the data lines. Do you have any pointers to discussions of the Amiga people using 3.3V SRAM at 5V, so I can check their experience?

The memory chip you suggest will not work. That's not asynchronous SRAM as required by 486 processors, but around 2 generations newer. They can be seen as the successor of pipelined burst SRAM. Their bus protocol is completely clock synchronous like the interface of SDRAM. They provide really high performance for systems that can use them, but a 486 mainboard just doesn't match synchronous ZBT SRAMs.

https://hackaday.com/2021/01/08/the-amiga-100 … comment-6309849
Afaik nobodys extension died in 2 years since https://www.amigalove.com/viewtopic.php?t=1689&start=50
is there anything driving the bus above 3V on 486 board? ram probably wouldnt, 3v cpu wouldnt, chipset?
sync/async is indeed no good 😀 I just sorted by price and speed. Still at 3.2ns there is plenty of time for fpga in between is someone decided to go that route.
So maybe ISSI IS61WV25616EDBLL-8TLI-TR, 8ns and 256 k x 16 to simplify board layout, max 4V + 0.5 so not that bad. 10ns version available at jlc https://jlcpcb.com/partdetail/948329-IS61WV25 … LL10TLI/C883296 to enable ordering already assembled board.

rasz_pl wrote on 2023-08-05, 09:35:

So maybe ISSI IS61WV25616EDBLL-8TLI-TR, 8ns and 256 k x 16 to simplify board layout, max 4V + 0.5 so not that bad.

I've already seen those x16 chips. using the full x16 bus width when substituting SRAM on 486 mainboards requires external logic. You need bytewise write enable, but reads must be unconditionally enabled for all bytes. These x16 chips do have byte enables, but they affect both the read and the write operation, and thus are incompatible with the interface between the cache controller and the cache chips. Of course, when you design your own cache controller, you will have no issues generating the signals to drive a x16 or x32 asynchronous SRAM (the 486 uses byte enable signals for both reads and writes on the FSB, so the signals are already there), but in this case I want to just emulate 32k x 8 / 64k x 8 / 128k x 8 asynchronous SRAM.

rasz_pl wrote on 2023-08-05, 09:35:

https://hackaday.com/2021/01/08/the-amiga-100 … comment-6309849

So they are using AS6C6416 chips on the Amiga 5V bus. The experience is likely transferrable to other 3.3V chips by Alliance of the same generation at least. Thanks for the link.

rasz_pl wrote on 2023-08-05, 09:35:

is there anything driving the bus above 3V on 486 board? ram probably wouldnt, 3v cpu wouldnt, chipset?

IIRC the scope traces showed that the chipset and the SRAMs at least are clearly driving to 5V (but they obviously don't show how hard it is driven). Normal PS/2 SIMMs also drive to 5V, but some of the latest PS/2 SIMMs use 5V-tolerant 3.3V RAM and dropper diodes (Z-Diodes?). Those SIMMs will not drive to 5V. Indeed, a 486 CPU will not drive 5V, but if you toast your AMD 5x86 at 4V to get 180MHz, you might get above the recommended operating condition of Vcc+0.3V with a Vcc of 3.3V. Likely, a 3.3V CPU is no practival issue with the 3.3V cache RAMs powered at 3.5V.

rasz_pl wrote on 2023-08-05, 09:35:

sync/async is indeed no good 😀 I just sorted by price and speed. Still at 3.2ns there is plenty of time for fpga in between is someone decided to go that route.

Using the sync burst option of these chips can be challenging because you need to set up linear burst / interleaved burst on them. This is a software-configurable option on latest-day 486 chipsets, but that won't reach to the cache module. So maybe a FPGA-based burst SRAM adapter needs to have a "Cyrix 5x86/ other" jumper? Cyrix 5x86 processors use signalling that is compatible with either linear or interleaved burst until you set the "linear burst enable" bit, so they can be booted with cache expecting linear burst even if the chipset assumes the processor is using interleaved burst.

Or you don't burst on the cache side at all, if the synchronous cache chips are fast enough to do non-burst access into a 60/66MHz 486 bus in a X-1-1-1 burst.

rasz_pl wrote on 2023-08-05, 09:35:

is there anything driving the bus above 3V on 486 board?

I just scoped the stuff:

• Address lines: (without active PCI bus masters): low: 0V, high: 3.6V (VCore is 3.6 or 3.7 at the moment).
• Data lines: Mixed high levels between 3.6V and 5V or somewhere in-between
• Control lines: /WE, /OE, /CE and the one address bit driven by the chipset: 5V

So it looks like there are CMOS-type drivers in the CPU (at Vcore) and the chipset (at 5V), and possible TTL drivers at other places. The RAM stick I currently have in that board uses 3.3V RAM with 2 diodes in series to drop the 5V operating voltage, so "in-between" level is likely originating in the RAM.

I do see overshoot to slightly above 5V on the address lines (measured near the cache chips). As I don't see the same amount of undershoot, it looks like the cache clamping over/undershoot to GND-0.3 to Vcc+0.3 or something like that. Overshoot spikes to 5V probably don't indicate any compatiblity issue with 3.3V RAM chips.

mkarcher wrote on 2023-03-13, 20:40:

mockingbird wrote on 2023-03-13, 00:07:

Fascinating tests... So far I am finding PCI 8881E/8886B (HOT-433) a lot more stable than the VLB VL/I-486SV2GX4...

That's comparing apples and oranges. The 8881E and 8886B are the last revision of the UMC 8881/8886 chipset, which is likely years newer than the SiS 471 on the VL/I-486SV2GX4. The SiS competitor to the UMC8881/8886 is the SiS 496/497. Again, the only latest revision of that chipset has EDO support. You can get VL-capable boards with both the SiS 496/497 (like the Lucky Star LS486E, the Soyo 4SA(W)2, the Asus PVI-486SP3) and the UMC8881/8886 (like the Gigabyte GA-486IM).

Would there be any reason to expect the SiS 496 to have much different performance in a cacheless+EDO DRAM configuration than the UM8881?

jakethompson1 wrote on 2024-02-21, 18:04:

Would there be any reason to expect the SiS 496 to have much different performance in a cacheless+EDO DRAM configuration than the UM8881?

I don't think so. I expect both chipsets to implement the same "industry standard" patterns to access EDO RAM. This also means you likely can use the publicly available datasheet for the SiS496 to get an idea how the UMC8881 accesses EDO RAM.

mkarcher wrote on 2024-02-21, 18:57:

jakethompson1 wrote on 2024-02-21, 18:04:

Would there be any reason to expect the SiS 496 to have much different performance in a cacheless+EDO DRAM configuration than the UM8881?

I don't think so. I expect both chipsets to implement the same "industry standard" patterns to access EDO RAM. This also means you likely can use the publicly available datasheet for the SiS496 to get an idea how the UMC8881 accesses EDO RAM.

Can we summarize the whole thread as: if you don't overclock, at 33 MHz the EDO RAM is capable of 2-1-1-1 but the DRAM controller isn't, so it is underutilized and you still need external cache to bridge the gap?

jakethompson1 wrote on 2024-02-21, 19:02:

Can we summarize the whole thread as: if you don't overclock, at 33 MHz the EDO RAM is capable of 2-1-1-1 but the DRAM controller isn't, so it is underutilized and you still need external cache to bridge the gap?

That is, essentially, the same problem early Pentium chipsets had: Re: IWILL P54TS Turbo switch

Unfortunately, we can't plug Pipeline Burst cache into 486. Yet.

Necroing this thread, as I got around to assemble another board (same PCB layout) with a set of CYC1009D-10 obtained from Mouser. Tested performance is slightly better. At FSB50, 3-1-1-1 works (this time I used the Am486DX4-120 i currently have in that board at 2*50, instead of the Am5x86-P75 at 3*50) in all tests (Dosbench Quake, Dosbench Doom, Running Stunts 4D sports driving and md5summing hard disk contents under Linux), which required 3-2-2-2 with the other board. As at the moment the A19 wire is broken off the board, I tested at 512K instead of 1M, but I don't expect that to make a difference (and if it does, it means the A19 wiring might be a problem).

At FSB60, it's still 3-2-2-2 or any DOS-like system crashes on boot.

I did not yet repeat the latency measurements. If I get around to do that, and I see interesting results (like an indication that the Mouser chips are indeed faster than the chips obtained from some possibly unreliable source), I will likely post scope traces showing the difference.

I think I have a set of CYC1009 waiting for this project's continuation. Where do I obtain the gerbers so I can order one of these PCB's?

A 256K version could also be helpful since 8 ns 32kx8 chips are obtainable.

feipoa wrote on 2025-05-04, 02:14:

I think I have a set of CYC1009 waiting for this project's continuation. Where do I obtain the gerbers so I can order one of these PCB's?

Your question finally pushed me to spend this day to clean up the schematics, port them to KiCad 9.0 and set up a GitHub workflow that automatically generates PDF schematics, a PDF variant of the PCB (for informational purpose only) and the Gerber file using presets targeted at JLCPCB manufacturing. See https://github.com/karcherm/mb8433-uud-cache- … leases/tag/v1.0 . Due to the automatic workflow, you can be sure that

• The schematics passes the electrical rules check (ERC) (except for explicitly suppressed violations). A report is automatically included in the release.
• The PDF schematic matches the KiCad schematic file(s)
• The PCB layout passes the design rules check (DRC) (except for explicitly suppressed violations). A report is automatically included in the release.
• The Gerbers match the KiCad PCB file

GitHub allows me to maliciously change the files after the automated workflow generated the correct files. You can't be sure I didn't do that. But you can be sure I don't upload old versions or versions that don't pass a rules check by accident, which is already "good enough" in my oppinion.

Excellent. Thank you. I am looking forward to comparing your PCB module with my more rudimentary 1024K adaption. It looks like all I need to do is press in the PCB and bodge wire the PCB pin marked "Connect CPU A19" to the CPU's pin A19. However, I noticed in your photos that the "Connect CPU A19" wire is actually a two-wire header. Are both wires meant to go to CPU A19, and if yes, why two wires and not one? I apologise if this has already been answered in the thread and I missed it, or forgot the details.

Any chance you will make a change to the gerber in the next few weeks? If not, I'll order the PCB now. It's only $2.

feipoa wrote on 2025-05-04, 23:18:

It looks like all I need to do is press in the PCB and bodge wire the PCB pin marked "Connect CPU A19" to the CPU's pin A19.

Exactly.

feipoa wrote on 2025-05-04, 23:18:

However, I noticed in your photos that the "Connect CPU A19" wire is actually a two-wire header.

The render in Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (terms and conditions apply) shows a angled 1-pin header. This header is at the top right in the first picture in Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (terms and conditions apply) , which is again only one pin. The PCB PDF (Biostar.MB-84xx-UUD.1MB.cache.module-assembly-1.pdf), it's the single hole in the very bottom right corner. I currently don't know how you got the impression that this is a two-pin header, but your confusion is completly understandable if it actually were a two-pin header.

The board has a couple of two-pin headers, but all of them are intended to be populated with IC header pins, as shown in your post Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (terms and conditions apply) . They generally go into pins 27 (/WE) and pin 28 (VCC) of DIP28 sockets, and are not meant to receive A19 from the CPU. The idea of populating only some pins that need to be popped into the board is not only to save money on connection pins, but it also makes insertion/removal easier, and it allows robust through-hole mounting of the connection pins between the SMD ICs.

Soldering the SOJ chips is difficult. The footprint I generated uses slightly shorter pads than the footprint that is nowadays included with KiCad. The newer footprint might ease manual soldering with an iron slightly, but applying it without re-routing some traces causes shorts on the board (it did happen to me when I just happily upgraded the symbol/footprint to the stuff delivered with new KiCad versions), that's why I include a dedicated SOJ32 footprint called "7.58" instead of using the nowadays included "7.62" footprint. That's also the reason why I use a custom "symbol" for the cache chips: The actual symbol has a footprint pattern that requires "7.6" to be included in the footprint name.

Ideally, you would use standard reflow soldering to mount the SOJ chips, this means applying paste using a stencil, preheating the board and then use hot air to perform the soldering. For manual hot-air soldering, I experienced it to be difficult to get enough heat below the chip (where the contacts are) without making the chip fly away. I finally decided to push them down with a heat resistant tool. Furthermore, adding solvent to dried 2 year old paste yields a suboptimal soldering experience. The chips are very close to each other and furthermore, U9 is also inconveniently very close to the edge of the board, so I'm sorry for the pain you are likely going to experience by building the PCB as is.

feipoa wrote on 2025-05-04, 23:18:

Any chance you will make a change to the gerber in the next few weeks? If not, I'll order the PCB now. It's only $2.

I don't intend to make any changes, although Disruptor suggested to re-route the tag chip in a way you can use an 8ns 32Kx8 chip (for 512K, which does not need A19 as well). That would be an untested change, though, so let me know whether you are highly interested in that modification. If yes, I can prepare that change. It doesn't seem too involved: I just need to route CPU A7 to pin 23 (currently grounded) instead of pin 31 of U9, and then I can run a thick trace connecting pins 30-32 of U9, supplying a sufficiently bypassed VCC to pin 30 (32-pin counting) / pin 28 (28-pin counting) of U9, so your EliteMT chips could fit there. I don't provide any warranty that these chips are specified or at least capable on working on 5V (the "L" in the model number is somehow suspicious, although it does not necessarily mean "3.3V"), though.

Oh, I think I get where you got the 2-pin header idea from: The last photo in Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (if your only other option is L2 at 3-2-2-2) - but I actually just used a 2-pin "dupont" socket-to-socket cable, because I had no 1-pin cable at hand to ground the A19 pin. The actual installation with the bodge wire, as shown in Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (if your only other option is L2 at 3-2-2-2) uses a single-pin socket on the cable.

My previous wording should not have been "two pin header", but rather "dual socket header connector". Your dual socket header connector with two wires is shown here: download/file.php?id=166485&mode=view Looks like you caught why I was confused in your most recent post.

Are the SOJ pads on your PCB even shorter than on Madao's Trio64V+ VLB card? Those are short as well, but can be managed with a bent fine tip stencil. If I get stuck, I do have a new unopened tube of solder paste I will use. I had ordered it for a batch of seven QFP-208's to be soldered.

Is it too time consuming to use the larger 7.62 footpring and re-route the affected traces?

I am equally interested in a 256K option. Would your modification be for 256K total, or just using an 8 ns 32kx8 as the TAG in a 512K configuration? I don't think I have enough 8 ns or 10 ns 64Kx8 chips. For this modification, would it be easier to create a second PCB for the 256K option rather than having fudge jumpers on a single PCB? The PCB's are cheap enough.

I don't know if the 'L' or 'LP' in LP61256GS-8 stands for "low power", but these SRAM chips did work fine on a Lucky Star LS-486 rev.D at 5 V.

feipoa wrote on 2025-05-05, 09:10:

Are the SOJ pads on your PCB even shorter than on Madao's Trio64V+ VLB card?

I think it's about the same.

feipoa wrote on 2025-05-05, 09:10:

Those are short as well, but can be managed with a bent fine tip stencil.

I struggled with them as well, but I finally got the Trio64V+ card assembled, using a classic iron with a fine tip. This method will clearly not work with my cache PCB, because the cache chips are way too close to fit a soldering tip in between. Maybe your bent fine tip will just do it.

feipoa wrote on 2025-05-05, 09:10:

Is it too time consuming to use the larger 7.62 footpring and re-route the affected traces?

Likely it's not that difficult, but yesterday I just wanted to get the project "publishing ready" and thus refrained from any unneeded modifications. That's also the reason why I have the special "NoSquare1" footprints for the pin headers. The new KiCad version has a bigger square solder pad on pin 1 (which is not really meaningful for the way I use these headers), which could get too close to some traces. I see no point in changing to the footprint with the square pin 1, while I do see a point in using the slightly wider SOJ footprints.

feipoa wrote on 2025-05-05, 09:10:

I am equally interested in a 256K option. Would your modification be for 256K total, or just using an 8 ns 32kx8 as the TAG in a 512K configuration?

The suggested modification would be 32kx8 TAG + 128kx8 DATA (possibly 64kx8 would work too, if A19 is routed to the "correct" pin on all chips, didn't check that).

feipoa wrote on 2025-05-05, 09:10:

For this modification, would it be easier to create a second PCB for the 256K option rather than having fudge jumpers on a single PCB? The PCB's are cheap enough.

I'm not thinking about jumpers, but about a minor modification that allows you to populate either a 128kx8 tag for 1024K, or a 32kx8 tag for 512K on the same PCB.

I suppose a 32kx8 tag option has some value if we can find those elusive 8 ns SRAM 64kx8 chips for the DATA. Do you recall if 10 ns 64kx8 SOJ SRAMs are obtainable from Mouser?

In order to get the timings as low as possible, I think a 256K option could be most beneficial, since 8 ns 32kx8 chips are available.

On a similar note, since I'll be using 10 ns 128Kx8 DATA chips, will I be able to use my sole 8 ns 64kx8 chip as the TAG? Or will some grounding or lifting of pins be needed?

feipoa wrote on 2025-05-05, 11:13:

Do you recall if 10 ns 64kx8 SOJ SRAMs are obtainable from Mouser?

No, I would have to look myself.

feipoa wrote on 2025-05-05, 11:13:

In order to get the timings as low as possible, I think a 256K option could be most beneficial, since 8 ns 32kx8 chips are available.

This would be a separate PCB, though. Keep in mind that the difference of the clock period between FSB40 and FSB50 is 5ns, and the difference between FSB50 and FSB60 is 3.4ns, which is more time than the 2ns gain when upgrading cache chips from 10ns to 8ns. So don't expect 8ns chips to generally allow at FSB60 what 10ns chips allow at FSB50, although if we currently miss the mark for FSB60 just be a small bit, 8ns chips might be "the solution".

feipoa wrote on 2025-05-05, 11:13:

On a similar note, since I'll be using 10 ns 128Kx8 DATA chips, will I be able to use my sole 8 ns 64kx8 chip as the TAG? Or will some grounding or lifting of pins be needed?

In the current state of the PCB, no. The 64k chip has one address pin less than the 128k chip, which will be pin 2 or pin 31. Currently, the unused address pin for the tag RAM is pin 23. If I reroute the tag chip to allow a 32k x 8 chip at 512K, I can easily choose whether the extra bit for 1024K is on pin 2 or pin 31. Would you mind looking up the data sheet for your 64k chip and tell me the functions of pins 1 (likely/hopfully "NC"), pin 2 and pin 31?

The 8 ns, 64kx8 SOJ SRAM that I have is an EliteMT LP61L512AS-8, shown here: download/file.php?id=165930&mode=view

I was never able to find a datasheet for it. Maybe it follows this pinout:

There seems to be quite a bit of variability in SRAM quality when it comes to pushing wait states at various frequencies. There's a user here who can seemingly cherry pick select SRAM modules to win the wait-state game. This is particularly problematic on the MB-8433UUD, stating that this board is very selective with SRAM chips of the same markings. I will likely do most of my testing at 60 and 66 MHz, hoping to get something better than 3-2-2-2. The M919 v3.4B/F can do 2-1-1-1 at 60 ns with the right SRAM and DRAM.

On the 8433UUD, I recall at 40 MHz, 1024K at 2-1-1-1 being problematic, whereas 256K had no problem. That was more than a decade ago, so I would need to redo all these tests. If a PCB for 256K is too troublesome, that's OK. 1024K 10 ns w/ 8ns tag is just as interesting.