Does it work cheaper Intel 440 chipsets, like 440zx/440lx/440ex?

marxveix wrote on 2026-04-28, 10:01:

Does it work cheaper Intel 440 chipsets, like 440zx/440lx/440ex?

Support for more chipsets will be added soon.

Code for chipsets are specific and pinned to them by there VID/DID.

Edit : half support is implemented. If you don't have a supported northbridge, but have a supported southbridge, you will see the setting for the southbridge. And vise versa.
If you configure for say the PIIX4, and later update for a new version that support the 440EX, then the configuration you did for the PII4X will be preserved.

Oh wow, this is something i really want to try out. My main retro system is a 430TX chipset which uses the Intel PIIX4 southbridge. I'm wondering what options are available to tweak.

Would be cool to have custom chipset register files like in TweakBIOS or wpcredit. This way users will be able to contribute files for various esoteric chipsets.

jheronimus wrote on 2026-04-28, 20:28:

Would be cool to have custom chipset register files like in TweakBIOS or wpcredit. This way users will be able to contribute files for various esoteric chipsets.

I do plan to have external files support in the future.
In the form of a binary format that would contain all the needed stuff.

It's not available yet as I'm not done with all the needed stuff (right now it only support registers in the PCI Configuration mode, no I/O registers or other fancy stuff).
Once I have all the stuff supported and all array structure defined and stable for everything, I plan to release a program that convert between text and binary (both directions)

The files will be in a "chips" subdirectory and UCP2 will scan theses to see if they support some of the present PCI devices.

The save format is already made in a way to support user modifications of registers definitions (it will still load and apply even if the definition get updated to add more stuff, and will also work if the order of the entries in the file change. Only saved stuff that is removed from the files don't get loaded/applied.).

Here is a current built-in file. Feel free to create new one and I can integrate it in the current version.

jheronimus wrote on 2026-04-28, 20:28:

Would be cool to have custom chipset register files like in TweakBIOS or wpcredit. This way users will be able to contribute files for various esoteric chipsets.

Here the support file for the PIIX4 :

Northbridge are.. more interesting but...
It have few ISA stuff, and a lot of IDE timing stuff (Backup your stuff before testing that please)

Rav wrote on 2026-04-28, 21:11:

Here is a current built-in file. Feel free to create new one and I can integrate it in the current version.

The attachment ali1541.c is no longer available

Nice! I'll try to mess with it on the weekend and add SiS 600, that one really benefits from this.

Note to people wanting to help submitting chip files.
PCI Configuration mode is accessed via 32 bits chunks and x86 is little endian. So here how to properly set the register

Example register 0x44, bit 2-3.
You take the register from the doc, 0x44, and do "mod 4". you endup with "0", so you do as simply as:
Register "0x44", mask "0C" and shift "2"

Example register 0x46, bit 2-3
0x46 mod 4 is equal to 2, so you have to shift all the stuff 2 times 8 bits on the left
You write it as register "0x44" still (You can also write 0x46, my program do chop the two last bits of the register digit.)
Mask would be "0x0C0000"
shift would be "18" ( 2 + (2 * 8 ))

Updated UCP2

- Simple hotfix to fix a bug in the screen configuration restoration (when user exit the TUI). It won't leave you with an invisible cursor anymore if you disable "UCP Settings > Restore screen framebuffer".
- Added part of planned IO Port type register configurations (nothing to see there, yet)

This is pretty cool stuff
Does it talk directly to chipset registers or uses a bypass?

StuckIn1999 wrote on 2026-05-05, 08:22:

This is pretty cool stuff
Does it talk directly to chipset registers or uses a bypass?

Right now it talk to the Chipset using the PCI Configuration Mode (IO at 0xCF8 / 0xCFC) and only support PCI chipsets.

The version I am working on can also talk to PCI adaptors and ISA devices via IO Ports ( It's going to be available soon including support for some S3 cards Pedestal bit fix mentioned here : https://bitsundbolts.com/2026/04/23/fixing-th … l-bit-bios-mod/ Funny enough I noticed that many of the S3 on 86Box have that bit enabled but they don't emulate the feature. ). Just doing some extra polishing and testing before releasing

UCP2 has been updated!

changelog:

- IO PORT support other than PCI Configuration mode supported
- ISA chipset supported (none implemented)
- PCI adaptors supported
- Save file format updated to support the IO Port stuff and ISA devices (Old format is converted to the new one if you already have a save file).

Added the following chipset
- 440EX
- 440FX
- 440LX
- 440ZX
- PIIX3
- PIIX

Added the following video cards
- S3 Trio64
- S3 Trio64 V2 DX
- S3 Virge DX

Rav wrote on 2026-05-05, 16:29:

The version I am working on can also talk to PCI adaptors and ISA devices via IO Ports ( It's going to be available soon including support for some S3 cards Pedestal bit fix mentioned here : https://bitsundbolts.com/2026/04/23/fixing-th … l-bit-bios-mod/ Funny enough I noticed that many of the S3 on 86Box have that bit enabled but they don't emulate the feature. ). Just doing some extra polishing and testing before releasing

Hi, @Rav,
With all my respect to the retro hardware repair work of @BitsUndBolts, his a.i. based videos are... let's say it this way - not a good source of reliable information. The last ones of his videos about S3 ViRGE and Trio3D video cards are just somehow working mumbo-jumbo shady exercises based on a.i. slop.

Briefly, here's what I have about so called "S3 BIOS bright bug":

For the older S3 cards based on Trio64V2/DX, ViRGE/DX, ViRGE/GX chips the "pedestal bit" in 0x03C5 register is this one: x x B x x x x x (the sixth bit if we count from the least significant bit starting from one). So, to cure the "bright bug" in the safest way, we have to use bitwise operation "AND 0xDF" (oxDF = 1 1 0 1 1 1 1 1) applied to the register 0x03C5. This way we don't change any other previously set bit values in the register.

1MOV	DX,3C4
2MOV	AL,8
3OUT	DX,AL
4INC	DX
5MOV	AL,6
6OUT	DX,AL
7DEC	DX
8MOV	AL,1A
9OUT	DX,AL
10INC	DX
11IN	AL,DX
12AND	AL,DF	; dis. BB
13OUT	DX,AL

The safest reverse bitwise operation enabling "bright bug" for the same older S3 card is with "OR 0x20" (0x20 = 0 0 1 0 0 0 0 0) applied to the same register 0x03C5. This way we don't change any other previously set bit values in the register.

1MOV	DX,3C4
2MOV	AL,8
3OUT	DX,AL
4INC	DX
5MOV	AL,6
6OUT	DX,AL
7DEC	DX
8MOV	AL,1A
9OUT	DX,AL
10INC	DX
11IN	AL,DX
12OR	AL,20	; en. BB
13OUT	DX,AL

Important note: The above dosn't apply to the very first ViRGE/325 (86C325) chip! Possibly due to different register's settings.

For the newer S3 cards based on ViRGE/GX2, Trio3D and possibly even Savage(4) chips the "pedestal bit" in 0x03C5 register is this one: x x x x B x x x (the fourth bit if we count from the least significant bit starting from one). In this case, to cure the "bright bug" in the safest way, we have to use bitwise operation "AND 0xF7" (oxF7 = 1 1 1 1 0 1 1 1). We don't change any other previously set bit values in this register.

1MOV	DX,3C4
2MOV	AL,8
3OUT	DX,AL
4INC	DX
5MOV	AL,6
6OUT	DX,AL
7DEC	DX
8MOV	AL,27
9OUT	DX,AL
10INC	DX
11IN	AL,DX
12AND	AL,F7	; dis. BB
13OUT	DX,AL

The safest reverse bitwise operation enabling "bright bug" for the same newer S3 cards is with "OR 0x08" (0x08 = 0 0 0 0 1 0 0 0).

1MOV	DX,3C4
2MOV	AL,8
3OUT	DX,AL
4INC	DX
5MOV	AL,6
6OUT	DX,AL
7DEC	DX
8MOV	AL,27
9OUT	DX,AL
10INC	DX
11IN	AL,DX
12OR	AL,8	; en. BB
13OUT	DX,AL

I hope the above examples are clear enough. I have assembled utilities for enabling/disabling the mentioned "bright bug" affected S3 cards, but this is topic for a new thread.

Thanks for your work on the chipset patcher tool!

EDIT: The correct "bright bug" register is 0x03C5, not 0x03C4.

aVd wrote on Yesterday, 04:58:

Hi, @Rav, With all my respect to the retro hardware repair work of @BitsUndBolts, his a.i. based videos are... let's say it this […]
Show full quote

Rav wrote on 2026-05-05, 16:29:

The version I am working on can also talk to PCI adaptors and ISA devices via IO Ports ( It's going to be available soon including support for some S3 cards Pedestal bit fix mentioned here : https://bitsundbolts.com/2026/04/23/fixing-th … l-bit-bios-mod/ Funny enough I noticed that many of the S3 on 86Box have that bit enabled but they don't emulate the feature. ). Just doing some extra polishing and testing before releasing

Hi, @Rav,
With all my respect to the retro hardware repair work of @BitsUndBolts, his a.i. based videos are... let's say it this way - not a good source of reliable information. The last ones of his videos about S3 ViRGE and Trio3D video cards are just somehow working mumbo-jumbo shady exercises based on a.i. slop.

Briefly, here's what I have about so called "S3 BIOS bright bug":

For the older S3 cards based on Trio64V2/DX, ViRGE/DX, ViRGE/GX chips the "pedestal bit" in 0x03C4 register is this one: x x B x x x x x (the sixth bit if we count from the least significant bit starting from one). So, to cure the "bright bug" in the safest way we have to use bitwise operation "AND 0xDF" (oxDF = 1 1 0 1 1 1 1 1). This way we don't change any other already set bit values in the register.

Working assembly code for disabling "bright bug" on S3 Trio64V2/DX, ViRGE/DX, ViRGE/GX

Copy code to clipboard

1MOV	DX,3C4
2MOV	AL,8
3OUT	DX,AL
4INC	DX
5MOV	AL,6
6OUT	DX,AL
7DEC	DX
8MOV	AL,1A
9OUT	DX,AL
10INC	DX
11IN	AL,DX
12AND	AL,DF	; dis. BB
13OUT	DX,AL

The safest reverse bitwise operation enabling "bright bug" for the same older S3 card is with "OR 0x20" (0x20 = 0 0 1 0 0 0 0 0) applied to the same register 0x03C4.

Working assembly code for enabling "bright bug" on S3 Trio64V2/DX, ViRGE/DX, ViRGE/GX

Copy code to clipboard

1MOV	DX,3C4
2MOV	AL,8
3OUT	DX,AL
4INC	DX
5MOV	AL,6
6OUT	DX,AL
7DEC	DX
8MOV	AL,1A
9OUT	DX,AL
10INC	DX
11IN	AL,DX
12OR	AL,20	; en. BB
13OUT	DX,AL

Important note: The above dosn't apply to the very first ViRGE/325 (86C325) chip! Possibly due to different register's settings.

For the newer S3 cards based on ViRGE/GX2, Trio3D and possibly even Savage(4) chips the "pedestal bit" in 0x03C4 register is this one: x x x x B x x x (the fourth bit if we count from the least significant bit starting from one). In this case, to cure the "bright bug" in the safest way, we have to use bitwise operation "AND 0xF7" (oxF7 = 1 1 1 1 0 1 1 1). We don't change any other already set bit values in this register.

Working assembly code for disabling "bright bug" on S3 ViRGE/GX2, Trio3D

Copy code to clipboard

1MOV	DX,3C4
2MOV	AL,8
3OUT	DX,AL
4INC	DX
5MOV	AL,6
6OUT	DX,AL
7DEC	DX
8MOV	AL,27
9OUT	DX,AL
10INC	DX
11IN	AL,DX
12AND	AL,F7	; dis. BB
13OUT	DX,AL

The safest reverse bitwise operation enabling "bright bug" for the same newer S3 cards is with "OR 0x08" (0x08 = 0 0 0 0 1 0 0 0).

Working assembly code for enabling "bright bug" on S3 ViRGE/GX2, Trio3D

Copy code to clipboard

1MOV	DX,3C4
2MOV	AL,8
3OUT	DX,AL
4INC	DX
5MOV	AL,6
6OUT	DX,AL
7DEC	DX
8MOV	AL,27
9OUT	DX,AL
10INC	DX
11IN	AL,DX
12OR	AL,8	; en. BB
13OUT	DX,AL

I hope the above examples are clear enough. I have assembled utilities for enabling/disabling the mentioned "bright bug" affected S3 cards, but this is topic for a new thread.

Thanks for your work on the chipset patcher tool!

Hi.

Yeah, in my code I only change the one specific bit.
I also did not try to patch it on the original virge.

I am going to add the code for the GX2 too for next update, thanks.

I just tried to briefly explain with tested and working examples, that the "pedestal bit" for S3 Trio64V2/DX, ViRGE/DX, ViRGE/GX chips in register 0x03C5 is one and the same, but differs from the "pedestal bit" for next generation S3 ViRGE/GX2 and Trio3D chips in the same 0x03C5 register. This is not clearly explained in the BuB's videos based on a.i. web searches.

I have an M1541/M1543 mainboard with a K6-2+, I'm already using CTU to enable write combining, MTRR and ordering - Are there any additional northbridge/southbridge settings accessible with this a[[ that can eek out a bit more CPU efficiency?