Reply 20 of 24, by Deunan
For 386 cache timings are simple, there is read and possibly separate write waitstate settings. 20ns chips should be enough for 33MHz unless the chipset is not very good. People often forget that there is a tag chip as well and it has to be checked first, so the timings of tag and data stack. This often means 20ns is just on the line with 40MHz operation and might not be fully stable, but also will not trip very often.
With 486 there are burst memory cycles, these are twice as fast as on 386 (there is only one addressing cycle). Which means both the cache chips and the chipset must be fast enough to present data on each cycle, rather than every second one. Most mobos deal with that by introducing extra WS or, if you have two cache banks, with interleaving. Though banking often slows down addressing, which means a 386/486 mobo can be made faster for 486 by populating both banks and going 3-1-1-1 (instad of 2-1-1-1), while 386 would prefer 2-x-x-x since it doesn't care about x (no burst) but 3- is way slower than 2- even with the extra bank of cache.
And then there are DLC chips that, for some reason, tend to trip the 20ns cache that worked OK with 386 and need 15ns. Point here is, it's often difficult to tell if the "it was working before" statement was actually true, it could have been marginal but not yet crashing. Any small change, including room temperature, can affect that. If in doubt always try 15ns chips, and the tag should be the first to be replaces (assuming it wasn't 15ns already). And in general if the mobo has two cache banks, populate both for 486.
