First post, by jakethompson1
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Breaking off from the Very Long Bus thread...
pshipkov wrote on 2021-10-10, 02:46:@jakethompson1 So, can you confirm if that board is really a carbon copy of VLI - perf-wise ? People need to sell kidney and kid […]
@jakethompson1
So, can you confirm if that board is really a carbon copy of VLI - perf-wise ?
People need to sell kidney and kid to afford VLI/PVI mobos these days.
Alternatives will be welcome.
Unfortunately I need to withdraw the recommendation for the 4DMS HL3G VI.
I got it out and was testing. Something is fundamentally broken with the handling of L1 WB CPUs. It seems like it's working but when you try to boot from a DOS floppy or format a floppy, nothing works. Disable L1 cache in BIOS (or switch to L1 WT) and it works fine.
The jumper settings in Total Hardware 99 and the GOEFA program are contradictory. The GOEFA directions for an Am5x86-P75 are for WT mode. The Am486DX4-120 directions produce the situation described above.
I tried using a multimeter to figure out the jumpers to no avail. There is a jumper that connects the INV pin to the CPU to the +5V supply with 0 ohms resistance; that makes no sense as INV is supposed to be a control line coming from the chipset. I don't think this would break anything though, just be less efficient than necessary as during snooping cycles it would always tell the CPU a device is about to write rather than read, possibly forcing the L1 cache line to be written back earlier than necessary.
The HITM# line from the CPU, on the other hand, doesn't seem to be connected to anything. Pin 90 of the 85C471 appears it's supposed to be connected to it, and indeed has continuity with pin A38 of the VLB slots. One of the unused jumper pins is connected to HITM#(apparently old Cyrix CPUs used that pin for SMI) so I tried running a wire from there to pin A38 of a VLB slot. No difference. I tried putting a resistor between pin A38 and A43 (ground) to force the chipset into always thinking the line is modified; also made zero difference.
Also tried these settings Am5x86 4x clock / WB and exhibits the same issue with formatting a floppy. DOS shows 0 percent complete then switches to track 0 bad, disk unusable. While it works fine with L1 cache turned off.
I also verified that chipset register 50h has the correct bit set for L1 write back control lines.
Anyone have ideas? I have no oscilloscope.