VOGONS


First post, by jakethompson1

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Breaking off from the Very Long Bus thread...

pshipkov wrote on 2021-10-10, 02:46:
@jakethompson1 So, can you confirm if that board is really a carbon copy of VLI - perf-wise ? People need to sell kidney and kid […]
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@jakethompson1
So, can you confirm if that board is really a carbon copy of VLI - perf-wise ?
People need to sell kidney and kid to afford VLI/PVI mobos these days.
Alternatives will be welcome.

Unfortunately I need to withdraw the recommendation for the 4DMS HL3G VI.
I got it out and was testing. Something is fundamentally broken with the handling of L1 WB CPUs. It seems like it's working but when you try to boot from a DOS floppy or format a floppy, nothing works. Disable L1 cache in BIOS (or switch to L1 WT) and it works fine.
The jumper settings in Total Hardware 99 and the GOEFA program are contradictory. The GOEFA directions for an Am5x86-P75 are for WT mode. The Am486DX4-120 directions produce the situation described above.

I tried using a multimeter to figure out the jumpers to no avail. There is a jumper that connects the INV pin to the CPU to the +5V supply with 0 ohms resistance; that makes no sense as INV is supposed to be a control line coming from the chipset. I don't think this would break anything though, just be less efficient than necessary as during snooping cycles it would always tell the CPU a device is about to write rather than read, possibly forcing the L1 cache line to be written back earlier than necessary.

The HITM# line from the CPU, on the other hand, doesn't seem to be connected to anything. Pin 90 of the 85C471 appears it's supposed to be connected to it, and indeed has continuity with pin A38 of the VLB slots. One of the unused jumper pins is connected to HITM#(apparently old Cyrix CPUs used that pin for SMI) so I tried running a wire from there to pin A38 of a VLB slot. No difference. I tried putting a resistor between pin A38 and A43 (ground) to force the chipset into always thinking the line is modified; also made zero difference.

Also tried these settings Am5x86 4x clock / WB and exhibits the same issue with formatting a floppy. DOS shows 0 percent complete then switches to track 0 bad, disk unusable. While it works fine with L1 cache turned off.

I also verified that chipset register 50h has the correct bit set for L1 write back control lines.

Anyone have ideas? I have no oscilloscope.

Reply 1 of 6, by jakethompson1

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Hmm seeming to have better results with Cx586 settings... those two faraway jumpers JP22/JP23 seem to play a role in INV/HITM#. This board is baffling.
That allowed the format to continue further but still 'general failure reading drive A' afterward. Steer clear of this board.

Reply 2 of 6, by TheMobRules

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On the 85C471, INV (A-10) is usually connected to the W/R# output pin of the CPU (N-17) for L1 WB. I don't think that chipset has an INV output pin.

Regarding HITM# (A-12) you are correct, it should be connected to pin 90 of the chipset for L1 WB.

Then there is WB/WT# (B-13), which should go to Vcc (+5V/+3.3V) for WB mode.

Additionally you have the CACHE# pin of the CPU (B-12), which in theory should connect to pin 118 of the chipset. But in the only SiS471 board I have with proper L1 WB support for the 5x86, setting this jumper makes the PC crash when booting from floppy. If I change the jumper to the other position, this CPU pin is connected to Vcc and L1 WB works fine on the 5x86.

Finally there is a trap that should be set on the chipset for L1 WB, usually this is done via a jumper, perhaps this is related to the register 50h you mention.

Reply 3 of 6, by jakethompson1

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TheMobRules wrote on 2021-10-13, 02:23:
On the 85C471, INV (A-10) is usually connected to the W/R# output pin of the CPU (N-17) for L1 WB. I don't think that chipset ha […]
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On the 85C471, INV (A-10) is usually connected to the W/R# output pin of the CPU (N-17) for L1 WB. I don't think that chipset has an INV output pin.

Regarding HITM# (A-12) you are correct, it should be connected to pin 90 of the chipset for L1 WB.

Then there is WB/WT# (B-13), which should go to Vcc (+5V/+3.3V) for WB mode.

Additionally you have the CACHE# pin of the CPU (B-12), which in theory should connect to pin 118 of the chipset. But in the only SiS471 board I have with proper L1 WB support for the 5x86, setting this jumper makes the PC crash when booting from floppy. If I change the jumper to the other position, this CPU pin is connected to Vcc and L1 WB works fine on the 5x86.

Finally there is a trap that should be set on the chipset for L1 WB, usually this is done via a jumper, perhaps this is related to the register 50h you mention.

Thanks. I guess INV -> +5V would just be a cheap design? The GOEFA says not to connect INV and +5V for Cyrix CPUs but to connect it for the other ones, ugh, more to experiment with.

I seem to have stumbled on what seems to be a working configuration. A mix of the Cx5x86 and Am486DX4 SV8B settings, *and* connect JP10 pin 1 [CPU HITM#] with JP13 pin 2 [chipset HITM#] or equivalently CPU HITM# with pin A38 on one of the VLB slots. I wonder how it was supposed to be possible to connect HITM# legitimately on this board? The only time JP10 pin 1 is ever jumpered is for Cx486 CPUs, which appear to use a different pinout where SMI was on the HITM# pin.

Without that jumper wire, FORMAT will get to 100%, but then say general failure, and every two seconds you hear the drive recalibrating. With the jumper wire in place, it works fine as it does when internal cache is off. Without the Cx5x86 jumper configuration (e.g. Am486DX4 SV8B) FORMAT will say track 0 bad and won't go past 0 percent.

Edit: Nope. No working L2 cache in the above configuration.

Reply 4 of 6, by pshipkov

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Reading your explanation and checking the usual data sources, it looks like the mobo supports only the early IntelDX4 (80486DX4) that have L1 cache in WT mode.
It must be something like that.
Still - bummer.

retro bits and bytes

Reply 5 of 6, by jakethompson1

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The problem seems to be identified. The INV line is indeed wired directly to +5V if you follow the jumper directions; the HITM# and CACHE# lines of a P24D pinout CPU are not connected to anything. In contrast, the HITM# and CACHE# lines of a P24T pinout CPU (Pentium OverDrive) are connected. They were supposed to be tied together per this spec (page B-4, http://datasheets.chipdb.org/Intel/x86/486/ap … ts/29043606.PDF) but are not.
It is possible to connect the HITM# line by being creative with the jumper settings. To connect the INV (properly to the W/R# output of the 471) and CACHE# lines requires soldering additional jumper wires on the underside of the board. I suppose I need to test the Phil benchmark pack and post the results.