Just spotted, are there a couple of bent pins around pin 41 of the Opti 82C571?

[edit: oh, and that unmarked jumper next to OSC1 is next to what would be the output pin, so maybe that's some sort of clock source select?]

maxtherabbit wrote on 2021-11-29, 22:28:

Just dropping in to say I love this motherboard, so cool

Thanks! I'm hellbent to get it running again!

snufkin wrote on 2021-11-29, 22:29:

Just spotted, are there a couple of bent pins around pin 41 of the Opti 82C571?

[edit: oh, and that unmarked jumper next to OSC1 is next to what would be the output pin, so maybe that's some sort of clock source select?]

No bent pins around the corner of pin 40-41 of OPTi 82C571 (found one slight bend on the other side though, nothing critical):

Regarding that jumper next to OSC1, yes it goes to the output pin of the socket (where the oscillator output would be, pin-8). With the current jumper setting I can trace it to pin 159 (out of 160) on the OPTi 82C571 chipset . Unfortunately I don't have such datasheet. What clock signal would such chipset want? 33 MHz, 66 MHz?

In the other jumper position, that clock signal would come from the adjacent SN74ABT245N Bus Transceiver chip (most likely connected with clock generator CH9007E on the receiving side):

maxtherabbit wrote on 2021-11-29, 22:28:

Just dropping in to say I love this motherboard, so cool

Same.
This board is a rarity. I wasn't aware of any s4 + s5 board at all.

Really hope you get it to work 100%!

I love this board. I have a quite a few S4 and S5 motherboard, but never seen one with both. It is an amazing find.

Fingers crossed that the board is actually fine and it was just that incompatible Matrox video card. In case it's useful I had a go a tracing the clock lines using the photo of the back of the board and it looks like at least four clock lines can select which clock source to use, but there's at least one that's always driven by the Chrontel main output. No idea what that means for how the jumpers should be set up. I'm slightly curious about what drives the bus enables for all those PI5C3884. Do they select which socket is connected?

I had a go a sketching it out the clocks (this includes guesses and may not be correct):

Green - 14.318 MHz reference
Yellow - CLK1 output and direct copies
Blue - Selected by jumper between Chrontel and OSC1
Purple - Guessing these are copies of the clock source selected by the jumper

snufkin wrote on 2021-11-30, 15:25:

Fingers crossed that the board is actually fine and it was just that incompatible Matrox video card. In case it's useful I had […]
Show full quote

Fingers crossed that the board is actually fine and it was just that incompatible Matrox video card. In case it's useful I had a go a tracing the clock lines using the photo of the back of the board and it looks like at least four clock lines can select which clock source to use, but there's at least one that's always driven by the Chrontel main output. No idea what that means for how the jumpers should be set up. I'm slightly curious about what drives the bus enables for all those PI5C3884. Do they select which socket is connected?

I had a go a sketching it out the clocks (this includes guesses and may not be correct):
ClockSelector.jpg

Green - 14.318 MHz reference
Yellow - CLK1 output and direct copies
Blue - Selected by jumper between Chrontel and OSC1
Purple - Guessing these are copies of the clock source selected by the jumper

Wow! That is some craftsmanship right there, thanks!

I have managed to trace the following clocks: reference, PCI / VLB [synchronus mode with 82C822 coming from 82C571] from pin 150 on 82C571 going to 82C822 inputs 80, 82 and 89.

I have not managed to trace how the main Chrontel clock reach the CLK input on the CPU (but I think your picture will help me) 😀

The R37, R36, R40, R35 goes straight to the PCI ports. This PCI clock is fed from the other side of the SN74ABT245N, coming from 82C572.

I guess the 82C572 is what is producing the 1/2 FSB : VLB/PCI clock ratio then? I have not found any other divider at least. Or possibly both 82C571 and 82C572 are capable of doing that since the 82C822 would not like full FSB speed as clock in synchronus mode.

So final piece of the puzzle is to trace how the main FSB clock reach the CPU CLK pin 📌

I will try to overlay some more traces on your picture, cheers!

This may be some slight help, it describes the early iteration of P54C socket 5 interfaces and explains the multiplier arrangement on the earliest steppings of P54 (i.e. why this board only has a 1.5x multi) but also has info on other matters that may pertain to this board, whereas the more common later docs floating around with pentium info, seem to miss out any info on the earlier pentiums (I guess they were "info on what we're shipping now, not what we shipped 2 years ago" tech docs)
http://bitsavers.trailing-edge.com/components … _Components.pdf

edit: by the way I wish I'd have seen this doc some years ago when I was messing around with a Siemens Nixdorf proprietary LPXish form all in one socket 5 board, because I had it working with a P90, then something happened to that, not sure whether it was assumed blown in another board or got used for something else, then came back to it with a P100 which may have been of a much later stepping and "mysteriously" couldn't get a peep out of it. So fairly sure I had a mismatch of capabilities there now. I am hopeful that one day that board resurfaces so I can beat it into submission with heavy knowledge. But it may have got tossed, cannibalized or improperly stored.

edit2: Checking your S spec this seems to be a C1 stepping P54 which uses the later method of multi control. Ergo I'd say you'd be more likely to boot the board with a B1 or B5 stepping CPU, I wanna say "gold top" is a cert, but thought I have also seen faster CPUs which should have been later stepping in that package, but 75/90/100 in that should work I think.

page was made:
https://www.ultimateretro.net/en/motherboards/9928

Specifications are largely taken from the only other similar board we know:
https://www.ultimateretro.net/en/motherboards/4989

BitWrangler wrote on 2021-11-30, 19:10:

This may be some slight help, it describes the early iteration of P54C socket 5 interfaces and explains the multiplier arrangeme […]
Show full quote

This may be some slight help, it describes the early iteration of P54C socket 5 interfaces and explains the multiplier arrangement on the earliest steppings of P54 (i.e. why this board only has a 1.5x multi) but also has info on other matters that may pertain to this board, whereas the more common later docs floating around with pentium info, seem to miss out any info on the earlier pentiums (I guess they were "info on what we're shipping now, not what we shipped 2 years ago" tech docs)
http://bitsavers.trailing-edge.com/components … _Components.pdf

edit: by the way I wish I'd have seen this doc some years ago when I was messing around with a Siemens Nixdorf proprietary LPXish form all in one socket 5 board, because I had it working with a P90, then something happened to that, not sure whether it was assumed blown in another board or got used for something else, then came back to it with a P100 which may have been of a much later stepping and "mysteriously" couldn't get a peep out of it. So fairly sure I had a mismatch of capabilities there now. I am hopeful that one day that board resurfaces so I can beat it into submission with heavy knowledge. But it may have got tossed, cannibalized or improperly stored.

edit2: Checking your S spec this seems to be a C1 stepping P54 which uses the later method of multi control. Ergo I'd say you'd be more likely to boot the board with a B1 or B5 stepping CPU, I wanna say "gold top" is a cert, but thought I have also seen faster CPUs which should have been later stepping in that package, but 75/90/100 in that should work I think.

That is one thick reference manual for the Pentium CPU 😀

It also covers the P5, so managed to locate the corresponding CLK pin for Socket 4. Nevertheless I could not find from where it gets the fundamental clock signal from, but I guess it must be from one of the chipset(s).

I did find the main clock input to 82C571 on pin 49, but nothing from there.

evasive wrote on 2021-11-30, 21:06:

page was made: https://www.ultimateretro.net/en/motherboards/9928 […]
Show full quote

page was made:
https://www.ultimateretro.net/en/motherboards/9928

Specifications are largely taken from the only other similar board we know:
https://www.ultimateretro.net/en/motherboards/4989

Now we are talking, thanks! One more for the archive then. I will try to fill in the blanks to the best of my knowledge.

mpe wrote on 2021-11-30, 09:11:

I love this board. I have a quite a few S4 and S5 motherboard, but never seen one with both. It is an amazing find.

Thanks! I will get this up and running again 😉

snufkin wrote on 2021-11-30, 15:25:

Fingers crossed that the board is actually fine and it was just that incompatible Matrox video card. In case it's useful I had […]
Show full quote

Fingers crossed that the board is actually fine and it was just that incompatible Matrox video card. In case it's useful I had a go a tracing the clock lines using the photo of the back of the board and it looks like at least four clock lines can select which clock source to use, but there's at least one that's always driven by the Chrontel main output. No idea what that means for how the jumpers should be set up. I'm slightly curious about what drives the bus enables for all those PI5C3884. Do they select which socket is connected?

I had a go a sketching it out the clocks (this includes guesses and may not be correct):
ClockSelector.jpg

Green - 14.318 MHz reference
Yellow - CLK1 output and direct copies
Blue - Selected by jumper between Chrontel and OSC1
Purple - Guessing these are copies of the clock source selected by the jumper

Regarding whether how all the PI5C3884 are wired and enabled, then I can confirm that both BE(A) and BE(B) are shorted to ground (regardless of the JP33 settings) - which are active-low (I.e., always enabled). This goes for all the PI5C3884 on either side of the Socket 5.

I'm sure they have something to do with the split signaling between Socket 4 + 5, so I need to trace the inputs/outputs to the sockets.

Additional, I can confirm that the JP33 is simply bridging Vcc (+5V) to the Gate of the TIP127 PNP Darlington transistor (serving as 3.3V voltage regulator), effectively meaning that it will be disabled (not output 3.3V) since it becomes a positively biased PNP transistor. What is interesting is that pin 1-3 and 2-4 (on JP33) are bridged permanently, so it wouldn't really matter if you put one (1-2) or both jumpers (1-2, 3-4) in place here (as suggested by the printing on the mainboard for P60/P66).

JP5 have something to do with the resistor configuration, so probably a means to adjust the output voltage from TIP127.

The jumper on the other side of the BIOS must be CMOS reset.

I have also confirmed that the Vcc to Socket 5 comes from the "output" of the TIP127 producing 3.3V, but it does not go to Vcc on Socket 4. Vcc (+5V) to Socket 4 is hard wired.

My guess is that I should probe for the CPU CLK pin going through one of the PI5C3884.

These jumpers JP1, JP2 and JP3 goes straight to BF0, BF1 and possibly to NC (future BF2) on Socket 5:

LocalBus wrote on 2021-12-01, 10:40:

Regarding whether how all the PI5C3884 are wired and enabled, then I can confirm that both BE(A) and BE(B) are shorted to ground (regardless of the JP33 settings) - which are active-low (I.e., always enabled). This goes for all the PI5C3884 on either side of the Socket 5.

That sounds weird. Why have them there if they're always on? And they have what look like pull up (or down) resistors on them. It seems like a lot of extra components and routeing work. Feels like there should be some way to disconnect them from Ground and then have the (I guess) pull ups turn the switches off.

My guess is that I should probe for the CPU CLK pin going through one of the PI5C3884.

Well, there's one obvious fat trace on Pin 23 (B9) of U4 that might be work a look at. They used large traces for the other clock lines, so maybe that's true here.

snufkin wrote on 2021-12-01, 12:01:

That sounds weird. Why have them there if they're always on? And they have what look like pull up (or down) resistors on them. […]
Show full quote

LocalBus wrote on 2021-12-01, 10:40:

Regarding whether how all the PI5C3884 are wired and enabled, then I can confirm that both BE(A) and BE(B) are shorted to ground (regardless of the JP33 settings) - which are active-low (I.e., always enabled). This goes for all the PI5C3884 on either side of the Socket 5.

That sounds weird. Why have them there if they're always on? And they have what look like pull up (or down) resistors on them. It seems like a lot of extra components and routeing work. Feels like there should be some way to disconnect them from Ground and then have the (I guess) pull ups turn the switches off.

My guess is that I should probe for the CPU CLK pin going through one of the PI5C3884.

Well, there's one obvious fat trace on Pin 23 (B9) of U4 that might be work a look at. They used large traces for the other clock lines, so maybe that's true here.

Spot on!

Managed to probe it from the back of the board and can confirm that the output from PI5C3884 to the thick trace indeed goes to CLK pin on Socket 5:

You can also see the adjacent somewhat thinner trace to goes underneath the CH9007E clock generator which is the corresponding input to PI5C3884.

I have not yet been able to probe continuity from the source (CLK1 on CH9007E) for this trace but I guess it goes via a capacitor or possibly transistor which must be enabled (e.g. controlled from chipset).

What is interesting is that the really thick clock trace takes a detour all the way to the edge of the board where the JP33 is placed for enabling/disabling the 3.3V voltage regulator. I'm sure there is something else to it since I couldn't probe the same CLK trace to the Socket 4.

So the next mystery to solve is how this Socket 4 is really enabled/disabled. Maybe just partly Vcc traces from +5V are passively on all the time, and where the JP33 are enabling the rest. Would explain why you have two jumpers if they must carry current 🤔

Note that in the picture orientation, the lower/bottom pins for JP33 (that you can see to the left) is the +5V Vcc, when these jumpers are bridged it then goes to the other thick trace, which for sure must go to some Vcc pins on Socket 4.

So somebody was making these piece of shit boards after the 34th week of 1994? (according to the Chrontel chip). That's incredible. I've seen a lot of 571/572 chips with VLB, but this the first time I've seen one with PCI. The OPTi PCI boards usually had the Python or the Viper chipsets. 571/572 was already obsolete in 1993. I'm surprised somebody had the nerve to use it in the second half of 1994.

This is one of those things that's so bad it's good. It looks stupid enough to be something sold by TMC/Mycomp, but according to the model name it probably isn't. Is this the only board that has both Socket4 and 5?

I hope you got some 8 or 9 chip FPM SIMMs for this thing. At least the 571/572 board I had was pretty particular about the memory used (as well as which banks were used).

Something just occurred to me about those PI5Cs. Those diodes next to each of them might control power to the Vcc pin. That way they don't have to route to both !BEA and !BEB, and just turn the power on or off. Drive pin 2 of the diode high to connect the bus, or let it float/drive it low and Vcc get pulled low through the 4.7k resistor (I'm assuming they go to Ground), disconnecting the bus. It's a bit rough, and can't think why they'd need a diode for that. Stop the bus switches switching off too quickly?

Might be worth checking what those diodes connect to, maybe a jumper?

Anonymous Coward wrote on 2021-12-01, 18:34:

So somebody was making these piece of shit boards after the 34th week of 1994? (according to the Chrontel chip). That's incredible. I've seen a lot of 571/572 chips with VLB, but this the first time I've seen one with PCI. The OPTi PCI boards usually had the Python or the Viper chipsets. 571/572 was already obsolete in 1993. I'm surprised somebody had the nerve to use it in the second half of 1994.

This is one of those things that's so bad it's good. It looks stupid enough to be something sold by TMC/Mycomp, but according to the model name it probably isn't. Is this the only board that has both Socket4 and 5?

I hope you got some 8 or 9 chip FPM SIMMs for this thing. At least the 571/572 board I had was pretty particular about the memory used (as well as which banks were used).

Haha I bet the original owner paid a premium for this along with P90 back in 1994 😄

Had Intel released any decent PCI chipset back then?

I found 8 MB modules from Electromyne that are on the way. Dual sided with 8 chips per side, FPM 60ns. Nothing fancy but I hope it will do the trick. Not sure why the are called PS/2 though? Something about compatibility?

Uh oh, PS/2 modules have the presence detect jumpers set different to standard.

snufkin wrote on 2021-12-01, 19:05:

Something just occurred to me about those PI5Cs. Those diodes next to each of them might control power to the Vcc pin. That way they don't have to route to both !BEA and !BEB, and just turn the power on or off. Drive pin 2 of the diode high to connect the bus, or let it float/drive it low and Vcc get pulled low through the 4.7k resistor (I'm assuming they go to Ground), disconnecting the bus. It's a bit rough, and can't think why they'd need a diode for that. Stop the bus switches switching off too quickly?

Might be worth checking what those diodes connect to, maybe a jumper?

Will do! The same idea did come across my mind; you simply turn off the PI5Cs completely instead of using the !BEA and !BEB inputs. It is a strange beast this one...

Relocated for a couple of days but I will pickup on this project again during the weekend, maybe I have received some SIMMs by then to test with 😀 I did find an old ISA Trident VGA card in my drawer, just in case the Cirrus Logic card takes some time to arrive.