Well, apologize for the stereotype.
Will blame it on limited imagination that portrays most members around here like:
40+ years old male.
Nice person.
Possibly glasses.
Possibly unshaved.

... Yesterday shirt (?!)

😉

pshipkov wrote on 2021-12-17, 17:59:

Well, apologize for the stereotype. Will blame it on limited imagination that portrays most members around here like: […]
Show full quote

Well, apologize for the stereotype.
Will blame it on limited imagination that portrays most members around here like:

... Yesterday shirt (?!)

😉

Yesterday's? You must be organised if you think that is old 😀

Comos wrote on 2021-12-14, 21:41:

Hi, […]
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Hi,

over the years I went through the board revisions which I have and Im looking the other ones to update my hardware list.
Currently I own the following revisions: 1.0, 1.2, 1.21, 1.6, 1.8. Beside that Im aware about rev 1.22 aswell.
Does somebody have a revision outside this list and can provide a picture please?

Hi, what revisions do your SiS chips have?
My 1.22 has 496:OR 9544 + 497:OT 9542
My 1.8 has 496:NV 9618 + 497:NU 9618

These are both B4 stepping which appears to be latest.

debs3759 wrote on 2021-12-17, 18:01:

pshipkov wrote on 2021-12-17, 17:59:

Well, apologize for the stereotype. Will blame it on limited imagination that portrays most members around here like: […]
Show full quote

Well, apologize for the stereotype.
Will blame it on limited imagination that portrays most members around here like:

... Yesterday shirt (?!)

😉

Yesterday's? You must be organised if you think that is old 😀

Hard dependency on marriage status there.

A certain factor in my household prohibits yesterday clothes. No way around it.
If such factor is not present in other households, then yesterday or last week is fine.

pshipkov wrote on 2021-12-16, 16:17:

Thanks.
I am not sure if the presence or absence of the jumper brings any evidence or has any meaning in general.

So what is the stepping of the boards you have.

The most of the revisions I have is 1.8 so have to go through all of them

have another Rev 1.22 for good measure:

Never saw a PVI with AV9155 clock generator.
Anyone ?
Remember looking at the av9155 datasheet, but it seemed incomplete. The listed frequencies didn't make sense.

pshipkov wrote on 2021-12-18, 07:23:

Never saw a PVI with AV9155 clock generator.
Anyone ?
Remember looking at the av9155 datasheet, but it seemed incomplete. The listed frequencies didn't make sense.

But with the VT8228 you can use a turbo switch with 3 contacts to switch from 40 to 25 MHz and back by connecting it to JP26 to it instead to a jumper.
Obviousely the VT8228 does the clock change so slow or soft that my AMD 5x86 133 and the rest of the system don't have a problem with the clock frequency change.

pshipkov wrote on 2021-12-18, 07:23:

Never saw a PVI with AV9155 clock generator.
Anyone ?
Remember looking at the av9155 datasheet, but it seemed incomplete. The listed frequencies didn't make sense.

I have it on rev 1.0, there is also a sticker with a correction for the jumpering above the original pcb printout.
However I got that mobo without a BIOS,but even when I put it from another one it won't POST,also according to the POST card appears to be dead.When I made futher investigation, the PLL does run,also the VRM,so probably the chipset is dead.
Need to find a nonor to get the board alive.This is the only revision which could have 1MB onboard cache,since in other revisions they limit it only to 512kB with the cache sockets altough with some modding it can be made back to 1MB with an onboard adapter.

Comos wrote on 2021-12-18, 10:20:

I have it on rev 1.0
...
This is the only revision which could have 1MB onboard cache,since in other revisions they limit it only to 512kB with the cache sockets altough with some modding it can be made back to 1MB with an onboard adapter.

Feipoa has found out (and me too) that the PVI-486SP3 does not allow tightest cache timings @ 40 MHz when just having one bank populated. So for maximum performance it is better to have 256 KB cache in 2 banks than having 512 KB in one bank.
So fully cached DRAM is just possible with 32 MB in L2 write back mode and 256 KB dual banked L2 cache.

Disruptor wrote on 2021-12-18, 10:33:

Comos wrote on 2021-12-18, 10:20:

I have it on rev 1.0
...
This is the only revision which could have 1MB onboard cache,since in other revisions they limit it only to 512kB with the cache sockets altough with some modding it can be made back to 1MB with an onboard adapter.

Feipoa has found out (and me too) that the PVI-486SP3 does not allow tightest cache timings @ 40 MHz when just having one bank populated. So for maximum performance it is better to have 256 KB cache in 2 banks than having 512 KB in one bank.
So fully cached DRAM is just possible with 32 MB in L2 write back mode and 256 KB dual banked L2 cache.

This was quite common on several 486 chipsets, that when banks are in interleave mode, it works best.

But it absolutely allows 40mhz with 512kb l2 cache and tightest timings easily.
That's one of its main qualities.
In fact it does it at 50mhz just fine too.
Mentioned it before in other threads - one of the very best 486 mobos out there.

pshipkov wrote on 2021-12-18, 15:59:

But it absolutely allows 40mhz with 512kb l2 cache and tightest timings easily.

I confirm this, based on my experience.

Good to hear I am not the only one here.