Looking around at jumpers near other KBCs, I think JP23 is probably reserved-keep open. The jumpers that crop up near KBC seem to be mono/colour, power save, CMOS battery related, and reserved. There's a Mitac board here that has the silkscreen "Reserved, Open": https://www.ultimateretro.net/en/motherboards/7208 where someone tested that it went to P16 on the KBC, which on the Intel 8042 is pin 33. So that matches yours.

That board may help a bit for IDing the remaining jumpers as it's also got an 822 fitted, although the main 2 chipset chips are different.

I've also finally realised that the CPU options given on your board (P60,66,90,100) will be talking about the original 5V Socket 4 P60/66. So that silkscreen now makes sense to me, with JP33 used to turn on Socket 4 and turn off Socket 5 when using a socket 4 P60/66. Nothing to do with a multiplier at all. I'd somehow got it in my head that this was a 486/586 socket 3/4 board (since the chipset can apparently handle both) and not a Socket 4/5 board.

Wonder if there's any way to adapt a 486 to work in a socket 4. Most of the pins are there.

snufkin wrote on 2022-02-10, 13:41:

Looking around at jumpers near other KBCs, I think JP23 is probably reserved-keep open. The jumpers that crop up near KBC seem […]
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Looking around at jumpers near other KBCs, I think JP23 is probably reserved-keep open. The jumpers that crop up near KBC seem to be mono/colour, power save, CMOS battery related, and reserved. There's a Mitac board here that has the silkscreen "Reserved, Open": https://www.ultimateretro.net/en/motherboards/7208 where someone tested that it went to P16 on the KBC, which on the Intel 8042 is pin 33. So that matches yours.

That board may help a bit for IDing the remaining jumpers as it's also got an 822 fitted, although the main 2 chipset chips are different.

I've also finally realised that the CPU options given on your board (P60,66,90,100) will be talking about the original 5V Socket 4 P60/66. So that silkscreen now makes sense to me, with JP33 used to turn on Socket 4 and turn off Socket 5 when using a socket 4 P60/66. Nothing to do with a multiplier at all. I'd somehow got it in my head that this was a 486/586 socket 3/4 board (since the chipset can apparently handle both) and not a Socket 4/5 board.

Wonder if there's any way to adapt a 486 to work in a socket 4. Most of the pins are there.

Yes it is a fully fledged VLB chipset so I think there is a good chance with a socket adapter to get a 486 running in there. The readable strings in the BIOS ROM lists 486 CPUs at least 😀

Now trying to figure out JP17, JP19, JP16 (they are not for presence detect). Probably linked with the 572 chipset, but they are all connecting to GND via R53, R52, R51.

So JP17, JP19 and JP16 are connected to pins 149, 152 and 153 respectively on the 82C572.

Some kind of bootstrapping I believe, looking at the Python chipset, they have a couple of pins called MP[7:0] setting various things upon reset, for example AT clock divider. But guessing wildly here since I don't have the actual datasheet.

These jumper input splits and goes both to the 82C572 and disappear underneath the SIMM slots (at the very upper edge of the board). No continuity on the memory pins at least.

Congratulations! Just wanted to let you know I followed this adventure almost day by day.

PD2JK wrote on 2022-02-10, 21:02:

Congratulations! Just wanted to let you know I followed this adventure almost day by day.

Thanks! It sure was an adventure, and so much great knowledge and support out there!!

Once the board is refreshed with new caps, transistors, oscillator and jumpers are all figured out - I must start thinking about a suitable chassis. Most likely a custom wooden chassis 😀

LocalBus wrote on 2022-02-10, 19:23:

So JP17, JP19 and JP16 are connected to pins 149, 152 and 153 respectively on the 82C572.

Some kind of bootstrapping I believe, looking at the Python chipset, they have a couple of pins called MP[7:0] setting various things upon reset, for example AT clock divider. But guessing wildly here since I don't have the actual datasheet.

These jumper input splits and goes both to the 82C572 and disappear underneath the SIMM slots. No continuity on the memory pins at least.

Just to check I've understood, the 3 traces come from the 572 pins, head to 3 of the jumper pins, then head off under the SIMMs somewhere. The other side of the jumpers each go through one of those resistors and down to ground? So if the jumper is fitted then the line will be pulled to ground, and if not fitted then it doesn't get pulled either way? What value are the resistors?

I'm going to guess that BC24 and BC25 are decoupling capacitors for the 572, so probably connect to its power pins. One side should measure short to ground, the other side will be a power supply. If those are strapping resistors then I'm wondering where the pull ups are so the line can be set either high or low. I'm thinking that maybe the device has internal pull ups, so try checking the resistance from each pin to whichever side of BC25 isn't ground.

Also, might be worth checking to see if those traces connect to the KBC. I'm also going to guess that the 572 is doing a similar job to the 547 you found the datasheet for. The 547 has an 🤣 bus (where the strapping pins are) that connects to various things, including the KBC, BIOS and 206. The jumpers are near the board edge, so it'd be fairly easy to just run them around the board edge to get the KBC and BIOS. Then run from the BIOS to the 206. Saves having to try crossing over the CPU/RAM/Local/ISA bus.

[edit: Hmm, missed that bb code turn XD in to a laughing smiley. Maybe that's appropriate in this case]

snufkin wrote on 2022-02-10, 21:34:

Just to check I've understood, the 3 traces come from the 572 pins, head to 3 of the jumper pins, then head off under the SIMMs […]
Show full quote

LocalBus wrote on 2022-02-10, 19:23:

So JP17, JP19 and JP16 are connected to pins 149, 152 and 153 respectively on the 82C572.

Some kind of bootstrapping I believe, looking at the Python chipset, they have a couple of pins called MP[7:0] setting various things upon reset, for example AT clock divider. But guessing wildly here since I don't have the actual datasheet.

These jumper input splits and goes both to the 82C572 and disappear underneath the SIMM slots. No continuity on the memory pins at least.

Just to check I've understood, the 3 traces come from the 572 pins, head to 3 of the jumper pins, then head off under the SIMMs somewhere. The other side of the jumpers each go through one of those resistors and down to ground? So if the jumper is fitted then the line will be pulled to ground, and if not fitted then it doesn't get pulled either way? What value are the resistors?

I'm going to guess that BC24 and BC25 are decoupling capacitors for the 572, so probably connect to its power pins. One side should measure short to ground, the other side will be a power supply. If those are strapping resistors then I'm wondering where the pull ups are so the line can be set either high or low. I'm thinking that maybe the device has internal pull ups, so try checking the resistance from each pin to whichever side of BC25 isn't ground.

Also, might be worth checking to see if those traces connect to the KBC. I'm also going to guess that the 572 is doing a similar job to the 547 you found the datasheet for. The 547 has an 🤣 bus (where the strapping pins are) that connects to various things, including the KBC, BIOS and 206. The jumpers are near the board edge, so it'd be fairly easy to just run them around the board edge to get the KBC and BIOS. Then run from the BIOS to the 206. Saves having to try crossing over the CPU/RAM/Local/ISA bus.

[edit: Hmm, missed that bb code turn XD in to a laughing smiley. Maybe that's appropriate in this case]

The jumpers JP17, JP19 and JP16 all short to GND on the bottom pin. The upper pin goes to the upper side of the corresponding resistor, then on the lower side it goes through a via, which on the backside splits to both the 82C572 and the follows the upper edge of the board to somewhere. You can see these three traces rejoining again just above JP17.

BC24 and BC25 are indeed decoupling capacitors.

Your reasoning makes sense, this is the AT controller chipset and yes to reach KBC and BIOS you would better route it along the edges. The probing goes on... 🤣

XD is appropriate here!

LocalBus wrote on 2022-02-10, 22:00:

The jumpers JP17, JP19 and JP16 all short to GND on the bottom pin. The upper pin goes to the upper side of the corresponding resistor, then on the lower side it goes through a via, which on the backside splits to both the 82C572 and the follows the upper edge of the board to somewhere. You can see these three traces rejoining again just above JP17.

BC24 and BC25 are indeed decoupling capacitors.

Ok, thanks for the photos. It looks like there are 8 lines going up around the edge, but two are on inner layers, I think. 3 traces come along under the 572, and 2 come up through vias between R51 and the board edge, but don't seem to go anywhere. You can see that the inner ground and power plane have been cleared from around their vias, and I can convince myself there's a shadow in the gap heading up with the other traces. Can you see if those vias connect to other pins near pin 150 on the 572. Although, looking further away, I think maybe they come from the 571.

So there are 1k (reasonably strong) pull downs and 8 wires. So XD seems possible, although if those 3 wires come from the 571 then maybe not. It'd also be interesting if you can measure the resistance from pin 149 to whatever the supply voltage on the 572 is then we can see if they have some pull up that gets overridden when a jumper is fitted. Still leaves the question of what they do. Maybe there's some diagnostic software you can use to find out what changes when you change the jumpers?

(Red is bottom layer, blue is top. There was a bit of a shadow, so I'm not sure I got the connections right around the jumpers).

The two vias on the opposite side of the resistors (near board edge) goes to pin 136 and pin 137 on the 82C571.

Pin 152 and pin 153 on the 82C572 reads 2.2kOhms to Vcc. Pin 149 reads 1.1kOhms to Vcc.

That looks odd, especially given the resistors going to the jumpers are all 1k, with the jumpers all going to Ground. If those lines are being used as inputs when the board starts then that would mean they were either 5V (jumper not fitted) or 2.5V (pin 149) or 1.7V (pins 152&153). Which doesn't look right.

Might be worth checking if any of 149,152,153 go to any control pins on some of the bus chips (74f245, pins 1 & 19). Looking at the top and bottom of the board near the battery, there are 3 think traces on the bottom that look to go to the KBC and 3 on the top, one of which looks like it goes to pin 19 of U45.

Pin 137 on 82C571 goes to PC speaker buffer, probed it all the way to the 33 ohm resistor I put aside. This is also aligned with the datasheet for the Python chipset (this is what gave me the idea to probe this in the first place). So probably a lot of similarities between the 82C571 and 82C547 😀

snufkin wrote on 2022-02-09, 18:29:

[forgot to say: Doornkaat wins the prize:

Doornkaat wrote on 2021-11-27, 19:24:

That's very cool!
Could the missing oscillator be the culprit?

]

Really? Woohoo!😄
But it wasn't just the oscillator, was it? This thread is twelve pages long after all.😅

Doornkaat wrote on 2022-02-11, 19:01:

snufkin wrote on 2022-02-09, 18:29:

[forgot to say: Doornkaat wins the prize:

Doornkaat wrote on 2021-11-27, 19:24:

That's very cool!
Could the missing oscillator be the culprit?

]

Really? Woohoo!😄
But it wasn't just the oscillator, was it? This thread is twelve pages long after all.😅

Haha yes, you got it from the starters! Beers on me!! 🍺

We somehow convinced ourselves that the chipset was sporting a 1/2 divider and that you could either use the Chrontel 9007E clock generator or an external oscillator as clock source. Hence I went and sourced a 66 MHz oscillator and yep, it "kind of worked" using either of them as clock source, which probably deviated us further from the goal 😀 I should have known better, since the jumper position it was in when I got it was indeed pointing at the non-populated oscillator (not even attempting to boot, no POST code). Then I changed the jumper using the CH9007E and started to see signs of life. Putting the 66 MHz oscillator in the socket and it "worked" with either clock source.

Turns out that the external oscillator had a very specific purpose for providing the clock for VL Chipset, VL Bus and PCI Bus. Not the FSB. And there is no such thing as a 1/2 divider in the chipset... now we know! 😉

While waiting for the 33 MHz oscillator to arrive I have been doing some additional probing just to make some sense out of all jumper settings.

Raw input as follows:

1BIOS ROM pin 19 [DQ5 | O5] -> 1kOhm (R28) -> JP15 -> GND
2
3BIOS ROM pin 10 [A2] -> (pin 7) [O6] 74F244PC (pin 13) [I6] -> 1kOhm (R25) -> JP12 -> GND
4
5
6JP9 (pin 1-2) -> pin 1 -> 4.7kOhm -> Vcc (5V) [pull-up], pin 2 -> A17 pin Socket 4 (and Socket 5 via PI5C) [trace splits from jumper also chipset, I guess it makes sense since it affects address line, not probed this end yet]
7
8JP9 (pin 3-4) -> pin 3 -> 10kOhm -> Vcc (5V) [pull-up], pin 4 -> A18 pin Socket 4 (and Socket 5 via PI5C) [trace splits from jumper also chipset, I guess it makes sense since it affects address line, not probed this end yet]
9
10JP8 pin 2 -> pin 1 U28 (cache package) && 10kOhm -> pin 1 74HCT245N (DIR)
11JP8 pin 1 -> A19 pin Socket 4 (and Socket 5 via PI5C) [trace splits from jumper also chipset, I guess it makes sense since it affects address line, not probed this end yet] 

JP12 and JP15 does indeed affect the BIOS ROM addressing.

JP8 and JP9 are somehow related to address lines && L2 cache. Surprised to see that these jumpers directly affects pull-up for A17, A18 and A19 on the CPU pins.

Can you install a 486 in this mobo using the socket 4?

I guess JP9 is cache size select, maybe JP8 disables the cache? No idea about JP12 & 15.

Sphere478 wrote on 2022-02-16, 21:12:

Can you install a 486 in this mobo using the socket 4?

Ha, I made the same mistake (I think) a couple of pages back, confusing Socket 4 with 486. Socket 4 was early Pentium. It looks like this board uses the Socket 4 for P60 and P66, and Socket 5 for P90 and P100. Which sounds like a pretty niche board. Can't have been that many people who either already had a P60 and wanted to buy a motherboard that allowed them to keep the existing CPU but also gave them a small upgrade path, or who bought both board and P60 intending to upgrade the CPU later.

The chipset supports 486 CPUs though. I had a quick look and I don't think Socket4 has all the Socket3 pins routed to it (e.g. A2, BS8#, BS16#), so I don't know what would be involved in trying to get a 486 working. Particularly given the complete absence of any chipset documentation.

Lessons learnt so far while getting acquainted with this board (up and running):

The BIOS allowed me detect up to 1807MB of my 4GB CF disk, not too bad, I was actually expecting less.

With an XT-IDE (AT) ROM loaded it happily detected the full disk (currently using a dedicated XT-IDE rev 4 card but will probably put this on a 3COM 3C509B boot rom later).

Next challenge then, trying to get a 32-bit PCI IDE controller up and running - no dice. I have a Promise Ultra 133 TX2 PCI card which indeed shows a message during boot up sequence that no drives were detected. Most likely due to the early PCI chipset on this board. Tried all kinds of PCI slots and IRQ allocation but no change. Also tried a semi-modern Silicon Image controller but that froze the system after memory check.

Reading up on the topic it seems there were just a few PCI IDE controllers at the time and all required a so called "paddle board" to be connected to the ISA bus anyways 🙄

Some say the performance was sub-par and you were better off with a 16-bit ISA IDE controller anyhow 😀

A contemporary controller (for 1994) for this board would have been the OPTi 82c621a with paddle board extension.

Still waiting for the 33 MHz oscillator but it seems stable enough at 40 MHz PCI / VLB clock actually.

If anyone have some tricks to get a modern PCI IDE controller up and running for a PCI 2.0 revision board, please let me know!

Try a promise tx4 sata II those seem to work in all my pentium boards

Sphere478 wrote on 2022-02-21, 22:31:

Try a promise tx4 sata II those seem to work in all my pentium boards

Thanks! I might just give it a try if I can get my hands on one.

How old Pentium systems are we talking about here? 430 chipset? I bet anything with PCI 2.1 compliance is somewhat more forgiving 😀

Have you tried testing combinations of JP32 and 34 in case they make a difference, since they seem to be connected to the VL/PCI bridge. Or the JP16/17/19 since I don't think we know what they do.