snufkin wrote on 2022-02-26, 14:04:

Sphere478 wrote on 2022-02-26, 05:31:

What if instead of moving the jumper, I lift the leg and run it over to the pad that it’s supposed to go to?

Not sure if that will change anything. The chip has 2 reference frequency outputs on pins 27 & 28. The one from 27 goes through R31, where it then splits with one branch heading back to where the 0 ohm link now is. If you were to lift pin 27 and connect it directly to the 0 ohm link then the only difference is that it bypasses the 100 ohm R31 resistor. That resistor is probably needed to terminate the clock net properly to stop ringing on the line.

Might be worth trying lifting pin 25. That's the one that's now a 48MHz output, and stops where the 0 ohm link used to be. Maybe that's causing some interference?

Like you said earlier, maybe it goes to more than one place, so maybe move the link back and re route the 14 mhz to the old 12 mhz spot?

Sphere478 wrote on 2022-02-26, 17:31:

snufkin wrote on 2022-02-26, 14:04:

Sphere478 wrote on 2022-02-26, 05:31:

What if instead of moving the jumper, I lift the leg and run it over to the pad that it’s supposed to go to?

Not sure if that will change anything. The chip has 2 reference frequency outputs on pins 27 & 28. The one from 27 goes through R31, where it then splits with one branch heading back to where the 0 ohm link now is. If you were to lift pin 27 and connect it directly to the 0 ohm link then the only difference is that it bypasses the 100 ohm R31 resistor. That resistor is probably needed to terminate the clock net properly to stop ringing on the line.

Might be worth trying lifting pin 25. That's the one that's now a 48MHz output, and stops where the 0 ohm link used to be. Maybe that's causing some interference?

Like you said earlier, maybe it goes to more than one place, so maybe move the link back and re route the 14 mhz to the old 12 mhz spot?

Ah, I see, so lift pin 25, put a short link from pin 27 to pin 25, then move the 0 ohm link back? Might be worth a try, although as far as I can see pin 25 only goes to the original position of the 0 ohm link. I don't think it will change much as depending on its position the 0 ohm link is either being driven from pin 27 (via R31) or from pad 25 (via the 22 ohm resistor between the 0 ohm link and the clock gen). My comment about it possibly going to more than one place was more wondering if it splits after the 0 ohm link and connects to something that only works at 12MHz and can't handle 14MHz.

You'd need to keep pin 27 and 28 soldered down as they definitely connect to other things on the board. Mind that pin 26 is a power pin, so check carefully for any short after soldering.

Given we don't know if the clock gen actually works properly then at this point I'd probably try reflowing all the pins, just to make sure. If that didn't work, then put the original clock gen back and check if it works with the 0 ohm link moved down (double checks that the KBC is ok at 14MHz). Then try with pin 25 lifted. If that worked then it would mean that the replacement clock gen should also work (i.e. anything on the 12MHz output works fine at 14MHz). So then try to replicate the C1 C0 fault by lifting each clock output in turn. If at some point you get the same C0 C1 failure then that might point toward an output not working on the replacement.

If you got a few of the replacement clock gens then you might also want to try one of those, with R48 removed. Maybe the one you currently have fitted has a broken output, or the 5V on pin 5/R48 caused some damage.

When I said the board worked with the jumper in the other position you understood that I was talking about the three pin jumper thruholes right?

Okay, well. What should I do next.. I’m getting nervous here..

Should I wait for the custom clock gen you guys are making?

Is there a way to stack clock gens and make this work? Old plus new? I don’t want to keep soldering on this board until something breaks

I have backup new clockgens. If you really think it was r48 that did this but I wanna be sure. Pulling that chip a bunch of times is asking for trouble

The legs are attached. I checked. (Several times)

Back in front of it,

Tried without ram. Same thing.
Gets to that stage and then glitches visually on diag card

Find someone with a fast scope and look at the signals. Not much can be done blindly guessing.

Yeah, getting a fast scope is the easiest way to tell if the clock gen is working correctly. Slowest it can be set for is 50MHz on the PClk outputs and 25MHz on the BClk.

I have had a go at tracing where all the clock outputs go:

Colours are:
Blue - PClk (set by pin 5,12,13. Leave 5 disconnected and fit J13 1-2 3-4 for 50MHz).
Yellow - BClk (half frequency of PClk, in phase).
Orange - 24MHz for chipset stuff (e.g. floppy controller).
Red - 48MHz USB (this was the 12MHz KBC signal on the original one).
Green - 14.318MHz reference.
Purple - crystal drive.

I've used dotted lines to show connections through resistors. I haven't bothered to trace out the delay lines that a couple of the Bus clocks and one of the Processor clocks go through.

The only output that should be any different from the 9159-02 is the red 48MHz signal. That goes through a 22 ohm resistor, then through an empty pad, then to the original location of that 0 ohm link. Moving the 0 ohm link disconnected that and connected to the green reference clock line instead. After the 0 ohm link the trace goes up to a via between the two RAM slots, where I then loose it (top-left in the picture). But it doesn't immediately split anywhere, so there's nothing to say that it does drive more than one device.

At the moment I'd speculate that there's something up with the clockgen. Only way I can think to test that without a scope is to put the original one back (leave the 0 ohm link where it is now), then try to recreate the fault by lifting each clock output pin in turn and see if you can recreate the fault.

snufkin wrote on 2022-02-27, 22:56:

Yeah, getting a fast scope is the easiest way to tell if the clock gen is working correctly. Slowest it can be set for is 50MHz […]
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Yeah, getting a fast scope is the easiest way to tell if the clock gen is working correctly. Slowest it can be set for is 50MHz on the PClk outputs and 25MHz on the BClk.

I have had a go at tracing where all the clock outputs go:
Tyan_S1564D_Clock2.jpg

Colours are:
Blue - PClk (set by pin 5,12,13. Leave 5 disconnected and fit J13 1-2 3-4 for 50MHz).
Yellow - BClk (half frequency of PClk, in phase).
Orange - 24MHz for chipset stuff (e.g. floppy controller).
Red - 48MHz USB (this was the 12MHz KBC signal on the original one).
Green - 14.318MHz reference.
Purple - crystal drive.

I've used dotted lines to show connections through resistors. I haven't bothered to trace out the delay lines that a couple of the Bus clocks and one of the Processor clocks go through.

The only output that should be any different from the 9159-02 is the red 48MHz signal. That goes through a 22 ohm resistor, then through an empty pad, then to the original location of that 0 ohm link. Moving the 0 ohm link disconnected that and connected to the green reference clock line instead. After the 0 ohm link the trace goes up to a via between the two RAM slots, where I then loose it (top-left in the picture). But it doesn't immediately split anywhere, so there's nothing to say that it does drive more than one device.

At the moment I'd speculate that there's something up with the clockgen. Only way I can think to test that without a scope is to put the original one back (leave the 0 ohm link where it is now), then try to recreate the fault by lifting each clock output pin in turn and see if you can recreate the fault.

Okay, so you’re my brain here on this mod, 🤣 so I’m understanding that you think there is a chance the new clock gen is a:fried by r48, b: fake and I have two options: a: install another new gen, b: install the old gen to make sure the board is still okay.

I don’t see it being likely that the board is bad, so installing the old gen will probably just confirm that. And the problem is probably the 14 mhz?

I think it’s possible that the new gen is fake or damaged, so installing a new new gen is just going to confirm wether or not r48 did something, but has the chance of actually turning this into a successful mod if that is what happened.

So make a judgment call for me here. Install a new gen, or install the old gen.

I want to avoid resoldering these pads as much as possible, so if there is a way to do this with as little resolders as possible lemme know.

I don’t have a scope that will work for this unfortunately. Or access to one.

Would it be better for me to stop here and start ordering parts for that other idea?

No matter what, I don’t want to damage this board.

Your call, tell me what to do next.

Excellent work on the traces btw!! Good job!

Ultimately it seems like the other idea is a better one we can provide the exact frequencies called for to the original pins and the board should be happy? What can I do to help with the other idea?

I put the old clock gen and resistors back in as they were.

It works again!

I may try putting that 0 ohm link back to do that test as you suggested, would installing that three pin jumper header also be able to do that? Been thinking about installing that just because it’s not there. Why not add it🤷‍♂️

I’m glad the board is okay, was worried there for a second.

Sphere478 wrote on 2022-02-28, 01:52:

Okay, so you’re my brain here on this mod, 🤣 so I’m understanding that you think there is a chance the new clock gen is a:fried by r48, b: fake and I have two options: a: install another new gen, b: install the old gen to make sure the board is still okay.

I saw you'd put the original back, which is what I was going to suggest, and that it still works, so that's good. I'm suspicious of the replacement clockgen, mostly because I can't see why it doesn't work. The only difference I can see is that the 12MHz output becomes a 48MHz output, but that doesn't go anywhere other than the original position of the 0 ohm link, so moving the link should just leave the 48MHz output disconnected.

I think the next thing to do is to try moving the 0 ohm link away from the original position, so it connects to the reference 14MHz output. For now I'd avoid putting in a jumper header as that'd probably cause some distortion of the clock signal. If it still works then maybe put in a 3 pin jumper header. The output pins would connect to the Red and Green pads on the clock routeing picture nearest the RAM and the middle pin to either of the two pads near the crystal.

Then check if it all still works if you remove R48. On the original clockgen that's an output enable input that should have an internal pull up, so it shouldn't need the external resistor.

After that then, in the absence of a fast scope, I think it's a choice between:
-lifting, testing and then reconnecting each output pin in turn and seeing if you can recreate the symptoms. That might show if it's one particular output that's not working on the new clock gen. That would at least suggest that the principal should work, you just had a duff part.
-jumping straight to trying one of the other spare new clockgen chips. Maybe a different one will work. Start out not connecting anything to pin 5, which should make it default to the same frequency selection as the original chip.
-waiting to see if someone can put together the clock synthesizer. Although that'll going to need a fast scope to check what the drive strength settings and general trouble-shooting.

Was clock generator IC sourced from chinese seller?

Then you have a fakes.

Cheers,

stop with fakes this fakes that. diag card suggests CPU was running = it generated frequency, but without proper diagnostics equipment its hard to tell what was missing

snufkin wrote on 2022-02-28, 22:38:

I saw you'd put the original back, which is what I was going to suggest, and that it still works, so that's good. I'm suspiciou […]
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Sphere478 wrote on 2022-02-28, 01:52:

Okay, so you’re my brain here on this mod, 🤣 so I’m understanding that you think there is a chance the new clock gen is a:fried by r48, b: fake and I have two options: a: install another new gen, b: install the old gen to make sure the board is still okay.

I saw you'd put the original back, which is what I was going to suggest, and that it still works, so that's good. I'm suspicious of the replacement clockgen, mostly because I can't see why it doesn't work. The only difference I can see is that the 12MHz output becomes a 48MHz output, but that doesn't go anywhere other than the original position of the 0 ohm link, so moving the link should just leave the 48MHz output disconnected.

I think the next thing to do is to try moving the 0 ohm link away from the original position, so it connects to the reference 14MHz output. For now I'd avoid putting in a jumper header as that'd probably cause some distortion of the clock signal. If it still works then maybe put in a 3 pin jumper header. The output pins would connect to the Red and Green pads on the clock routeing picture nearest the RAM and the middle pin to either of the two pads near the crystal.

Then check if it all still works if you remove R48. On the original clockgen that's an output enable input that should have an internal pull up, so it shouldn't need the external resistor.

After that then, in the absence of a fast scope, I think it's a choice between:
-lifting, testing and then reconnecting each output pin in turn and seeing if you can recreate the symptoms. That might show if it's one particular output that's not working on the new clock gen. That would at least suggest that the principal should work, you just had a duff part.
-jumping straight to trying one of the other spare new clockgen chips. Maybe a different one will work. Start out not connecting anything to pin 5, which should make it default to the same frequency selection as the original chip.
-waiting to see if someone can put together the clock synthesizer. Although that'll going to need a fast scope to check what the drive strength settings and general trouble-shooting.

Okay,

I’ll probably dig into it in next day or two. Thx! 😀

I can at least try moving those resistors to see if we can learn something.

rasz_pl wrote on 2022-03-01, 00:31:

stop with fakes this fakes that. diag card suggests CPU was running = it generated frequency, but without proper diagnostics equipment its hard to tell what was missing

pentiumspeed wrote on 2022-03-01, 00:12:

Was clock generator IC sourced from chinese seller?

Then you have a fakes.

Cheers,

Yeah, we really don’t have conclusive evidence of a fake here. It’s possible still though, but we can’t say that yet. I’m betting that it’s more likely that r48 fried it. Or we missed something.

Finally!! Some dual socket 7 overclocking!!

Any luck with the custom generator idea?

I'm considering making a pcb project for this

a small pcb that solders to the board where the old clock gen went that allows a different one to be used.

thoughts?

what would be a easy to find clock gen to base it off of that has many fsb options? i think it would be nice to find one that has a lot of small steps. 66, 86, 70, 73, 75, 80, 85, 90 examples. etc..

or has there been any progress with the idea about the tunable generator?

i have a fear that the tyan in dual may not have a whole lot of overclocking headroom. I know 430hx often was able to do 75-83mhz but the two processors may cut into that?

anyway. thoughts?

stamasd wrote on 2022-02-15, 23:17:

So here's some testing with the SI5351 clockgen. Nothing very exciting yet, just confirmation that it actually works, that it ca […]
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So here's some testing with the SI5351 clockgen. Nothing very exciting yet, just confirmation that it actually works, that it can generate precise clocks and that 2 signals derived from the same PLL are in fact phase-synced.

The setup: Arduino and generator board. Ignore the transistor on the right, that's part of another project.

Waveforms at 50 and 25MHz. I had to fiddle with the settings a lot because my probes aren't exactlty high quality. Also the 50MHz is skirting on the limits of my oscilloscope, so I turned on some automatic smoothing of the curves.

And because of that for testing I fiddled with the code and halved the above, to 25 and 12.5MHz respectively, and turned off smoothing, so these are closer to the real waveforms.

I think these would be adequate to drive the PCLK and BCLK signals, probably through some buffers.

And the bad news: the 3rd output, the one I had calculated for 14.318MHz - was way off. It gave 8.256MHz instead. I probably messed up the calculations somewhere, but I'm too tired to double check now.

And on a final note: yes I know my phone camera is shit, but there isn't much I can do about that.

this seems very promising, can we do more testing with this?

do you have data sheets for these? footprints?

do you plan on doing testing with this on the tyan?

found this datasheet

https://learn.adafruit.com/adafruit-si5351-cl … t/circuitpython

more infos^

I'm trying to find a footprint for these pcbs. not having much luck.

the si5351 clock generator and the Arduino nano. or whatever the smallest one is that will drive the si5351 clock generator is.

-

-

Did some tinkering...
I still need exact footprints and better measurements. this is kinda eyeballing it.

open to suggestions on how to tap the original chip's pads. it seems that the board needs to be elevated. attaching resistor legs seems like a possibility and hovering the whole contraption above the board may be possible, but not easy. and I worry about the pads breaking.

I assume we can power the thing from the 5v?
will the usb need to be plugged in whenever setting it or can we program it then use a jumper block?

Looking for ideas with this

🤔

I'm tired so I might not be taking everything in correctly at the moment.

However I have seen from my time tinkering with old apple laptops that there do exist sockets that fit to surface mount pads. I have no idea what they are called but apple used them in their powerbook g4's a few times. I think it was for their built in modems, don't remember for sure.

I would worry about signal integrity though.

too tired to think of anything useful at the moment.

https://learn.adafruit.com/assets/18754

Also, that may help with your pads.

Centers of the mounting holes are 25.4 mm apart, you can see one is on the 11th column and the other is on the 21st column.
It looks to me that the left and right most pads for the sma connectors are centre aligned with the mounting holes. So centre to centre of the left and right most pads would also be 25.4mm (roughly but close enough).

It looks like that's what you were trying to lay out above so I thought I'd pass my input along.

I also had a check for stock. LCSC has the chip in stock, JLC does not.

I do have a question though.

Is your goal to completely replace all the clocks on the socket 7 board or just give the user more control over the FSB?

CalamityLime wrote on 2022-05-20, 19:24:

I do have a question though.

Is your goal to completely replace all the clocks on the socket 7 board or just give the user more control over the FSB?

Well, full control of pci, isa, and fab would be ideal. At some point we need to find out if they must be synchronized though, (did we answer that yet?) if so can they be synchronized at different fractions or only the standard ones.

Anyway. Fsb is the major consern. I suspect that these boards may be able to run as high as 83mhz stable but we have no way of trying to do so.

Would be nice to be able to overclock a dual processor setup 😀 also running k6 at 500mhz would be nice