we still dont know if second Cout is needed at all now
Not needed.
if you have too much time you could experiment taking small caps out one at a time, down to leaving just one per side :)
lol, I'm already wondering when divorce papers are going to spontaneously appear on my desk. I want to wrap this up. With just the removal of those 11 extra decoupling ceramics sphere wanted, I created another short. I suspect 4 is minimum and 8 is a good middle ground, in fact, 8 will be almost completely symmetrical.
One can continually try to improve and re-improve for months, like it is some glorified wall nick-nack, but I'm going to be calling it quits soon. If someone else wants to perfect this to an absurd level, they can take over the testing.
they arent useful for decoupling
That's kinda what I figured. Thanks.
:( I should have specified looking for correlation means zoom all the way in and see if jaggies on 3V line correspond to 5V ones and vice versa, looking if load spikes on one side influence the other.
I ran thru several time scales and all were good. Nothing periodic on the 200 mV division I was using. When I had D22 shorted to Vcc and the screen stayed blank, I did notice a very small periodic noise at 200 KHz, like something was trying to reset itself or get out of certain state.
1) can you please increase the separation between the VRM's GND solder pad and the 5V plane on the VRM's Vin next to the GND pin? Basically, shrink the 5V plane right around VRM's GND pin. This is the third time I've shorted this. No issue with the other pins. If people are going to assemble these, this issue will probably come up.
Im not a fan of 0.2mm clearance everywhere, 0.4 is fine when not pushing traces between socket pins
Wanna go to staggered pin?
No. If you don't want to shrink the 5V plane around the VRM's GND pin, I can work around it, but future assemblers will not be happy.
Let me know what package type you want to use for c in and c out.
Why are we talking about changes here? Dual tantalums seem the safest option. See below.
pentiumspeed wrote on 2022-12-06, 16:14:
Silkscreen is labels to denote the locations or labels for components. The insulating mask is what covers the copper leaving pads and solder vias bare for soldering. Also yes, needs via or two for each pad for large MLCC capacitor, Yes, have to reroute the tracks around the ground and VCC vias.
I need to clarify, less tantalums, more large ceramic MLCC similar size as previous tantalum in the centre area.
Tell me what exactly what capacitance you want on those four Cout or Cin pins and I will run the test for you.
At what point will we upset the "not too low ESR" warning noted in the MIC's datasheet for Cout? I think it didn't want less than 500 mOhm for Cout but didn't seem to care much about Cin. Curiously, the LP datasheet says it wants less than 500 mOhm for Cin, but Cout can be whatever.
Will having ceramics in the centre region violate this 500 mOhm warning? Or are they far enough away from the VRM not to cause a problem? Or will they only not cause a problem if their capacitance is low enough, like 1-100 nF?
I haven't had time to remove the latest tests from my camera. It takes a very long time to crop, resize, name the files so I can find them, etc.
Plan your life wisely, you'll be dead before you know it.