Let me know what package type you prefer for cin on bottom. A flat ceramic if it will work sounds perfect. Do tests, we will go with whatever gives best waveform.

See if you can come up with a capacitor combo that involves 21 decouplers, 2 cout, 1c in.

Less decouplers is fine. But Based on what we saw I think more the better. If even in the local area of the pins. As we may not see distortion at regulator. May have to probe the empty cap/LIF pins themselves to see the distortion.

Here is latest. (Yes I know, but I have time right now 🤣 and most importantly, motivation!)

I’m liking rounded like you suggested.

I don’t like the third half length option I think the risk of short extends to the whole pad because it will be manipulated more than the others because of the cap.

Let me know what package type you prefer for cin on bottom. A flat ceramic if it will work sounds perfect. Do tests, we will go with whatever gives best waveform.
[/quote]
I will see if there's a flat pack, but ideally there would be nothing there whatsoever. So far, clearances are already tight, or touching. I can test for double caps by piggybacking the tantalums to see if any improvement.

Sphere478 wrote on 2022-12-06, 06:47:

Less decouplers is fine. But Based on what we saw I think more the better. If even in the local area of the pins. As we may not see distortion at regulator. May have to probe the empty cap/LIF pins themselves to see the distortion.

I do intend to probe a few of the non-decoupled Vcc pins. At the moment, I think it best to continue testing with the VRM installed. Like maybe there's no noise on the decoupled pins with the external DC supply, but noise with the VRM. To save effort, I should install the VRM now.

Sphere478 wrote on 2022-12-06, 06:47:

I don’t like the third half length option I think the risk of short extends to the whole pad because it will be manipulated more than the others because of the cap.

Only an issue for the novice solder, I'd speculate. But in that case, the novice would be buggering up several of the through-hole pins. If you want to make it more novice proof, you could add small SMD pads between the through-hole vias. I don't think it would mess with the plane that much...?

You sir, appear to posses greater solder skill than I 🤣

I figured out how to make the model more complete.

I tried making pads larger. More square. But it did mess with plane and routing so I went back to round

I'm gonna upload this to save my place. not releasing. You can download if you want to look, but I'm not calling it ready yet. :

Sphere478 wrote on 2022-12-06, 07:06:

You sir, appear to posses greater solder skill than I lol

More like learning ones limits and how to get around them. Get yourself some 2.25x - 3.25x reading glasses and work using those, even if you think you have the close-up eyesight of a 10 year old. The 10x from strap-on gem magnifiers usually have too much magnification for general SMD work and don't always do both eyes very well simultaneously, at least not the ones I have. The other trick, is when doing fine soldering that any amount of shake will goof it up, hold your breath until the solder hardens. Don't drink any caffeine. Don't do any work until the whole house is asleep. Also, if you are getting older and have shaky hand, find a means of bracing it. To avoid shadows, bring the light in at an angle that won't create a shadow. First do a lousy 'tack weld" to hold the item in place, then do the otherside properly, and then the 'tack weld' side properly.

Sphere478 wrote on 2022-12-06, 07:06:

You can download if you want to look, but I'm not calling it ready yet.

I don't want to install KiCAD 6.0 on my older Ubuntu setup since KiCAD v6 it is not part of the package repository and does not have a snap app. It can be forced if you confirm the dozen warnings you see, but not for my precious AsRock 939Dual SATA2 w/AM2 card system. I hate nothing more than fixing Linux issues (actually wait at emerg. for 20 hrs w/kids is worse). In general, you can often break your fixes with a new base update. Don't ask me how I know. I once spent days getting some obscure Chinese USB wifi card working with a particular kernel sub-version only to have the next base update ruin it. Spent several more days trying, but no luck. I could revert the sub-version, but then I'd be out updates for the rest of the release period. Ultimately, I spent more money to get a better supported wifi solution for my garage desktop system.

👍

- we still dont know if second Cout is needed at all now
- not a fan of silk screen as insulator under caps
- the only thing I would change is bigger Pin 1 solid silkscreen triangle

Sphere478 wrote on 2022-12-06, 03:10:

Thoughts on this added ground plane? (Bottom of pcb)

there was nothing wrong with ground as is 😀

Sphere478 wrote on 2022-12-06, 03:10:

The 5 v plane is basically a ring

I instinctively go no rings, no loops, but Im not a layout engineer 😀

feipoa wrote on 2022-12-06, 03:46:

Personally, I'd only add silkscreen to the 10 locations I identified. More symmetry, more pleasing to the eye. W don't know if those extra 11 Vcc-Gnd locations provide any improvement. If they aren't necessary, let's save people some effort with assembly. If it helps, I can solder caps on to those extra 11 locations to see if it does anything to the waveform.

if you have too much time you could experiment taking small caps out one at a time, down to leaving just one per side 😀

feipoa wrote on 2022-12-06, 03:46:

But for the direct-pin cap soldering, what would happen if I put ten 100nF 0805 tantalums to the pins instead of ceramic? Unfortunatley, I only have 10 uF tantalums on hand in 0805.

bad things, tantalums lose capacitance at high frequencies https://www.researchgate.net/figure/Capacitan … _fig4_229019152 and their ESR doesnt go down with frequency
https://www.johansondielectrics.com/tantalum- … -and-esr-curves
they are a good output cap electrolytic replacement (providing bulk capacity), they arent useful for decoupling

feipoa wrote on 2022-12-06, 03:46:

Since we are doing revisions right now, I think swapping the sides the Cin and Cout are on would be neater. In my opinion, Cout should be near the voltage-set trimmer, rather than the other side of the VRM.

yes

feipoa wrote on 2022-12-06, 03:46:

Do you all think that the 5v Cin cap needs to have the current channeled through the pad like cout? Or is it okay like is?

I don't think so, provided Cout is right at the VRM's input. Rasz_pl may have more input on this though.

yes, but still not a layout engineer! 😀

feipoa wrote on 2022-12-06, 04:39:

Yes I have several images showing the 5V line, some pages back. It will be the blue coloured line. I can connect CH2 again for continued testing, just it was creating more effort connecting/disconnecting. 5V was clean.

Scope is showing a larger width of 10.0 ms to try and catch more noise peaks, but my standard of 250 us looks similar.

🙁 I should have specified looking for correlation means zoom all the way in and see if jaggies on 3V line correspond to 5V ones and vice versa, looking if load spikes on one side influence the other.

Sphere478 wrote on 2022-12-06, 04:43:

As far as I know, voltage needs spark gap and amps need cross section and cooling. Amps are what induce signals in near by wires through inductance voltage, by leakage. We honestly aren’t dealing with much of amps or volts here. But the 5v plane definitely doesn’t cary as much current as the 3.3v plane.

yep

feipoa wrote on 2022-12-06, 04:39:

I haven't had time to remove the centre caps yet. I will first remove the centra caps, then snap a waveform. Then add the 13 extra caps, snap a waveform. Then add the LP regulator, then swap for MIC regulator.

first test LP with and without center caps

feipoa wrote on 2022-12-06, 07:00:

At the moment, I think it best to continue testing with the VRM installed. Like maybe there's no noise on the decoupled pins with the external DC supply, but noise with the VRM. To save effort, I should install the VRM now.

yes!

Sphere478 wrote on 2022-12-06, 06:28:

Squared or round🤔image.jpg

neither, pull the copper away from pin holes

feipoa wrote on 2022-12-06, 07:00:

you could add small SMD pads between the through-hole vias. I don't think it would mess with the plane that much...?

yes!

edit: fixed missquote

You mis quoted that last one.

I tried modifying the pads and clearances. It causes other issues. Clearances are so tight. Cover it in silk, done. Problem solved.

5v being a ring was pretty unavoidable with the way traces are routed I had to use blue layer unless I was to use far more vias for the signal traces. Earlier in the thread I routed without using blue layer but the traces had vias everywhere.

I could make 3.3v a cross board plane but then it would be over the densely packed traces in center region. Feiopa seems to have proved that these rings work though with decoupling caps.

Sphere478 wrote on 2022-12-06, 12:33:

You mis quoted that last one.

fixed 😀

Sphere478 wrote on 2022-12-06, 12:33:

I tried modifying the pads and clearances. It causes other issues. Clearances are so tight. Cover it in silk, done. Problem solved.

I was thinking

Sphere478 wrote on 2022-12-06, 12:33:

5v being a ring was pretty unavoidable with the way traces are routed

imo you dont need such big 5V plane, can limit it to half pcb closer to regulator and its still 12 pins going straight from motherboard, rest can become another ground or be used for signals

Its all nitpicking at this point 😀 You did fantastic job designing this interposer!

Pic: Well that might not be so bad on the top, It’s going to butcher the conductive cross section on the sides. We are thin enough on 5v as is imo

Also there are a few traces on the 5v plane that that would run into

I'll have to reply to inquiries in depth tomorrow. I ran out of time. Short form,

1) can you please increase the separation between the VRM's GND solder pad and the 5V plane on the VRM's Vin next to the GND pin? Basically, shrink the 5V plane right around VRM's GND pin. This is the third time I've shorted this. No issue with the other pins. If people are going to assemble these, this issue will probably come up.

2) Having extra tantalums makes matters worse. I'll provide photos later. You will want to ditch all the centre cap zones and the second Cout you added.

3) There's an average of a 8 mV noise loss on a per-pin basis when adding a 100 nF to a Vcc3-GND pair, however I did not witness any average noise reduction benefit to the VCC3 plane. In fact, just adding these extra 11 caps, I plugged in the unit and it didn't work. The solder bridge between D22 and Vcc was only visible after very close inspection at 10x and an hour wasted. Personally, I think the increased risk of shorting pins does not outweigh any potential noise benefit. Anyone adding 21 decoupling caps to a 386 should have their priorities checked out by a psychiatrist. Once the PGA132 pin headers are in place, removing these shorts become extremely frusturating. I wish the diameter of the heads on the pin headers wasn't so large.

4) The LP branded VRM can take the voltage up to 4.86 V, so in this regard, it is an improvement over the MIC, which I think could do 4.65 V, however this was with much noise. I need to re-compare the two VRMs again.

5) Just checking a single pin pair, if we put a 10 uF ceramic in place of the 100 nF ceramic, the noise reduces further. But what would happen if we added 21 10 uF ceramics to these pins? Would the ULDO no longer function as desired?

6) Note that adding 21 ceramics hasn't been fully tested for functionality. I had D22 shorted to VCC3 when I ran it and measured the noise as such. The computer wouldn't turn on because of this. I had to remove every one of those extra 11 caps to find the short and I don't think I want to resolder them due to the hidden short risk.

7) I'm forgetting some information, and will fill in later after I edit through the photos.

rasz_pl wrote on 2022-12-06, 13:28:

fixed :) […]
Show full quote

Sphere478 wrote on 2022-12-06, 12:33:

You mis quoted that last one.

fixed :)

Sphere478 wrote on 2022-12-06, 12:33:

I tried modifying the pads and clearances. It causes other issues. Clearances are so tight. Cover it in silk, done. Problem solved.

I was thinking
cap pads.png

That's also what I was thinking.

Sphere478 wrote on 2022-12-06, 13:50:

Pic: Well that might not be so bad on the top, It’s going to butcher the conductive cross section on the sides. We are thin enough on 5v as is imo

measure cross section circumference of LDO 5V pin - thats all the copper between LDO and 5V from the motherboard at the narrowest point. It doesnt matter if you make 5V floodfill half the board if its going thru a single pin anyway.
It does matter for 5V CPU to connect with many pins because it presents AC load (capacitive?) and more pins reduces impedance, but LDO is mostly DC? all the switching load is hidden behind LDO

Sphere478 wrote on 2022-12-06, 13:50:

Also there are a few traces on the 5v plane that that would run into

dont quite understand that part. Im looking at B.cu layer, bottom half is looping +5V fill, can be removed/replaced with ground fill
we dont need 20 decoupling caps, I believe even just 4 will be fine, one on each cpu side. K2 R8 K16 B9

In fact I would go as far as removing 5V fill altogether replacing it with ground pour, and just do one 5V track between G2 G3 and LDO input.

feipoa wrote on 2022-12-06, 14:28:

1) can you please increase the separation between the VRM's GND solder pad and the 5V plane on the VRM's Vin next to the GND pin? Basically, shrink the 5V plane right around VRM's GND pin. This is the third time I've shorted this. No issue with the other pins. If people are going to assemble these, this issue will probably come up.

Im not a fan of 0.2mm clearance everywhere, 0.4 is fine when not pushing traces between socket pins

CPU *is* noisy means AC around the DC voltage and yes this will show on LDO's out pin too. Less tantalums around three is fine, but needs more MLCC on the pads.

Silkscreen is labels to denote the locations or labels for components. The insulating mask is what covers the copper leaving pads and solder vias bare for soldering. Also yes, needs via or two for each pad for large MLCC capacitor, Yes, have to reroute the tracks around the ground and VCC vias.

I need to clarify, less tantalums, more large ceramic MLCC similar size as previous tantalum in the centre area.

Cheers,

Wanna go to staggered pin?

Let me know what package type you want to use for c in and c out.

I had figured we could use two tantalums of half spec to equal one. The routing characteristics with two is superior. I’m trying to keep two if we can. But if we really need to we can ditch it.

we still dont know if second Cout is needed at all now

Not needed.

if you have too much time you could experiment taking small caps out one at a time, down to leaving just one per side :)

lol, I'm already wondering when divorce papers are going to spontaneously appear on my desk. I want to wrap this up. With just the removal of those 11 extra decoupling ceramics sphere wanted, I created another short. I suspect 4 is minimum and 8 is a good middle ground, in fact, 8 will be almost completely symmetrical.

One can continually try to improve and re-improve for months, like it is some glorified wall nick-nack, but I'm going to be calling it quits soon. If someone else wants to perfect this to an absurd level, they can take over the testing.

they arent useful for decoupling

That's kinda what I figured. Thanks.

:( I should have specified looking for correlation means zoom all the way in and see if jaggies on 3V line correspond to 5V ones and vice versa, looking if load spikes on one side influence the other.

I ran thru several time scales and all were good. Nothing periodic on the 200 mV division I was using. When I had D22 shorted to Vcc and the screen stayed blank, I did notice a very small periodic noise at 200 KHz, like something was trying to reset itself or get out of certain state.

1) can you please increase the separation between the VRM's GND solder pad and the 5V plane on the VRM's Vin next to the GND pin? Basically, shrink the 5V plane right around VRM's GND pin. This is the third time I've shorted this. No issue with the other pins. If people are going to assemble these, this issue will probably come up.

Im not a fan of 0.2mm clearance everywhere, 0.4 is fine when not pushing traces between socket pins

Wanna go to staggered pin?

No. If you don't want to shrink the 5V plane around the VRM's GND pin, I can work around it, but future assemblers will not be happy.

Let me know what package type you want to use for c in and c out.

Why are we talking about changes here? Dual tantalums seem the safest option. See below.

pentiumspeed wrote on 2022-12-06, 16:14:

Silkscreen is labels to denote the locations or labels for components. The insulating mask is what covers the copper leaving pads and solder vias bare for soldering. Also yes, needs via or two for each pad for large MLCC capacitor, Yes, have to reroute the tracks around the ground and VCC vias.

I need to clarify, less tantalums, more large ceramic MLCC similar size as previous tantalum in the centre area.

Tell me what exactly what capacitance you want on those four Cout or Cin pins and I will run the test for you.

At what point will we upset the "not too low ESR" warning noted in the MIC's datasheet for Cout? I think it didn't want less than 500 mOhm for Cout but didn't seem to care much about Cin. Curiously, the LP datasheet says it wants less than 500 mOhm for Cin, but Cout can be whatever.

Will having ceramics in the centre region violate this 500 mOhm warning? Or are they far enough away from the VRM not to cause a problem? Or will they only not cause a problem if their capacitance is low enough, like 1-100 nF?

I haven't had time to remove the latest tests from my camera. It takes a very long time to crop, resize, name the files so I can find them, etc.

No worries.

I’m just working on other project atm. I can pick this back up.

So back to one cin and one c out both on top. Got it!

And more clearance around the regulator easy stuff. Was just asking if staggered would be easier. 😀

So it sounds like waveform gets better the more decoupling is added all the way to 21?

Okay, I personally am insane. And in that case will install them on mine. Haha :p so a Compromise is simply to release a 8 silk and a 21 silk version when I release the gerbers. 😀

Okay,

So your wish list:

-Back to one c in one c out. Same capacitor footprint. It shal be done 😀

More clearance and protection around the regulator pads.
About the problems with the those….
I almost forgot but I mentioned this earlier in theead. I actually found and corrected mask clearance there. So I actually may have already fixed that. I think you’ll find that the mask didn’t go all the way to the pad. It does now. So I think it is already fixed. But I can also add silk.

I think mask clearance (already fixed on latest version) and silk will do the trick for sure. Acceptable?

So the new version will have two tantrums, and 8 decoupling caps.

Anything I am missing? Anything else? 😀

Sphere478 wrote on 2022-12-07, 02:10:

So it sounds like waveform gets better the more decoupling is added all the way to 21?

Hmmm... did I say that somewhere? If so, can you point me to the typo and I can edit it. So far, there was no net average improvement of 21 caps over 10. I am going to take it down to 8 and check again. EDIT: ahhh, only slightly better on a per-pin basis, but not as an average. EDIT2: if you want even better per-pin, wait for the results and discussion.

Sphere478 wrote on 2022-12-07, 02:10:

Anything I am missing? Anything else? :-)

I like what rasz_pl did with the decoupling caps. If not possible, forget about it.

I have a few more days of testing.

Yesturday's photos coming soon...

Before I start shrinking images in GIMP, I wanted to share this brief moment of brilliance I had this evening. We keep our butter in the fridge, including the garlic butter. I know some people leave these on the counter, but we don't. So my wife as asking if I could have some toast and garlic butter ready with leak soup. I don't know how she does it, but she can plop the toast in the toaster then put the butter right onto the bread and it would melt. I tried this in the past, and I can never get the butter to melt. I usually get fed up and put the toast with unmelted butter into the microwave. But my wife doesn't want the toast soft, which is what microwaving does.

Then it dawned on me that the hot air station heats up rather quick and I'd be able to localise the heat onto just the butter. Seemed to work, and no complaints!

Some of us make ramen in the coffee pot man.

feipoa wrote on 2022-12-07, 02:39:

Hmmm... did I say that somewhere? If so, can you point me to the typo and I can edit it. So far, there was no net average impro […]
Show full quote

Sphere478 wrote on 2022-12-07, 02:10:

So it sounds like waveform gets better the more decoupling is added all the way to 21?

Hmmm... did I say that somewhere? If so, can you point me to the typo and I can edit it. So far, there was no net average improvement of 21 caps over 10. I am going to take it down to 8 and check again. EDIT: ahhh, only slightly better on a per-pin basis, but not as an average. EDIT2: if you want even better per-pin, wait for the results and discussion.

Sphere478 wrote on 2022-12-07, 02:10:

Anything I am missing? Anything else? 😀

I like what rasz_pl did with the decoupling caps. If not possible, forget about it.

I have a few more days of testing.

Yesturday's photos coming soon...

Sorry man, there is a lot of info in this thread and a lot of posts I’m tryin to keep up, doin a thousand things here.

If I forget or mis quote just remind me 😀

I’m searching posts for what rasz_pl did with decoupling caps. I forgot what they did? Do you mean with the flat on one side round on other pads? I know that will cause issues on some of the locations, but let me see if it could work for 8 locations?🤔

I see where he wanted me to pull back the 5v plane. Might work, but I feel iffy about pulling from so few pins. I also see more possible problems from that and no real benefit. What if mobo didn’t route those well?

Gonna try and make a better marking for pin one like requested

Pulling copper away from decoupling cap/socket pins may be less of an issue than square pads. But also has issues of reducing cross section.

I’ll stand by for your updates and conclusions.

Here is the baseline with the LP38503TSX-ADJ installed. Blue is CH2 and is Vin (VCC5). Yellow is CH1 and is Vout (VCC3). VCC5 noise is 136 mV. VCC3 noise is 72 mV:

Removing those 4 tantalums from the centre region, which were 22 uF, 470 nF, 150 nF, 220 nF:

Noise on Vcc5 mostly disappears, or down to 48 mV and the noise on Vcc3 remains about the same. Here's the lower freq view:

And the higher freq view:

Next, I am comparing the noise on the B9 pin, which is Vcc3 and does not have a 100 nF cap, with the noise on the B11 pin, which has a 100 nF cap. The B11 pin w/cap is YELLOW-CH1 and the B9 pin without cap is BLUE-CH2.

At the 200 mV scale, the noise on the two is about the same, but if you keep watching the average Vpp measurement, there does appear to be slightly less noise with the B11 pin which has the cap.

Zooming in to a 100 mV/division scale, that difference becomes a little more apparent, perhaps an 8 mV average difference.

Next, I wanted to see what would happen if I added a 10 uF cap to the B9 pin and left B11 with 100 nF.

The 48 mV previously witnessed on pin B11 w/100nF shrinks to 40 mV.
The noise on pin B9 without caps at 56 mV shrinks 36 mV with a 10uF cap. It begs the question, can a VRM not wanting too low of ESR on Vout take 8x or 10x MLCC 10 uF caps on the PGA pins provided that the tantalum is still in place on either side of the VRM?

Next I went on to fulfil sphere's wet dream of an asymmetric cap forest. I used 100 nF caps:

The result, measured at the VRM, but with data pin 22 shorted to Vcc, showed no net improvement on Vcc3 as a whole. Still at 72 mV. Once the sockets are in place, it is too easy to get shorts under the pin headers when adding the caps, so I won't be running this again. I suspect we will still see 72 mV.