Sphere478 wrote on 2022-12-10, 03:02:

Looking at this closer, I can add more on the underside without much sacrificing also. Again, on the 5v though […]
Show full quote

Looking at this closer, I can add more on the underside without much sacrificing also. Again, on the 5v though

Do you want more 5v caps?

Thicker pcb will mean less interference and suck pins in more.

It will also increase via resistance.

Give and take.

I think 1.6 makes sense unless 2.0 is same price and even at that, a toss up

Edit: managed to fit 10 5v 1210 caps above and below without much sacrificing of design.

Want all of em? Or take some out?

Aren't there traces crossing the bottom central region? If not, or can be moved, it sounds like a decent plan to put the 4x Vin on the bottom and 4x Vout on the top. Only one minor drawback to putting the caps on the bottom centre region is they will be more difficult to remove on/off for experimenting. Not a show stopper though.

10? lol. I think 4 Vin and 4 Vout are enough. It is really diminishing returns. I think best to stick with the values and quantities tested.

Here is my stopping point for now let me know if something needs changed. I added all possible cap points. they don't need to be used. not a release, just for looking 😀

That's some slick looking spaghetti. Should be no problem having unpopulated solder pads on the inside bottom. Maybe U1 and U2 will fit there as well. Only 1 person will ever use those. Were you able to get those 0805 solder pads on for those 8 PGA caps?

u1/u2 are most ideal near the pin header. I actually improved those during the update. less vias in critical areas now.

all 21 PGA caps have D shaped pads. but they are the same width as the circular pads. we can't bring them closer or it will cut the copper there.

Is cutting the copper in 8 places that bad of a move? I may be mistaken, but I thought you had done so at the 8 locations identified previously?

Now that we are keeping the central cap pads, I don't need to further test 10 uF at the PGA pins - after all, it didn't improve the waveform. I am wondering if there is any value in testing sub-100nF caps on a few of the other PGA pins.

Looking in my bin, I have:
10 nF, albiet in 0603 but manageable
0.22 nF, albiet in 1206 but manageable
0.047 nF in 0805

I ran a few more tests with 47 pf, 10 nf, 220 pf additions. I don't think they helped much. As always: Blue is Vin, Yellow is Vout.

All tests have the 8 central caps installed.

Here is the baseline configuration with 8x 100 nf at PGA pins:

Next I add 4x 10 nf at PGA pins, one on each side:

Same as above, but showing that the 2.5 KHz waveform is still sort of there. Measure from centre of those spiky peaks to centre:

Next I add another 4x 47 pf caps. Does it seem like the amplitude of those spiky peaks decreased ever so slightly?

Next, I add 3x 220 pf, the system boots but hangs while loading all my DOS autoexec commands. We are at 19 caps now. This phenomenum is repeatable. Previously, I tried 21 x 100nf caps and system stayed at blank screen. For this configuration, too many PGA caps = no bueno. For your interest, this is what the waveform looks when the CPU has stalled out, and I assume would be the most optimal noise level we could achieve with the existing design.

It seems to me that the 8x 100 nF caps are already optimised and continuing on with up to 16 PGA caps is like splitting the hair you've already split.

feipoa wrote on 2022-12-10, 08:26:

Is cutting the copper in 8 places that bad of a move? I may be mistaken, but I thought you had done so at the 8 locations identi […]
Show full quote

Is cutting the copper in 8 places that bad of a move? I may be mistaken, but I thought you had done so at the 8 locations identified previously?

Now that we are keeping the central cap pads, I don't need to further test 10 uF at the PGA pins - after all, it didn't improve the waveform. I am wondering if there is any value in testing sub-100nF caps on a few of the other PGA pins.

Looking in my bin, I have:
10 nF, albiet in 0603 but manageable
0.22 nF, albiet in 1206 but manageable
0.047 nF in 0805

These are in the largest conductive path for vcc5 which is the main conductive path left after the shrink. I had not done more than D shaped pads previously. See the green and black pictures of what silk looks like after gerber generation to see what pads look like. I recently have done it a better way though that only makes the pads that shape on blue 5v layer. Which helped routing in center layers

Okay. Here is the plan

The design has changed enough that the unit you are testing may no longer be relevant.

So pour over this latest as best you can and I will do the same over next day or two. If all looks good we are gonna prototype it. For now I will leave all pads but tests on this new design will determine how many we will remove. I think there have been too many changes not to do one more prototype.

Do you see anything that needs changed?

I returned the pot back to the previous wiring btw.

feipoa wrote on 2022-12-10, 02:55:

Cost aside, would there be any benefit to producing the PCBs in 2 mm height so that the PGA pins won't stick as far down under the PCB? And if there are signal traces stacked on one another without any grounding between, could this extra thickness help at all?

no, and you should snip those legs flush after soldering, they do all act like mini antennas

>on the 5v though

10 caps on the input is pure insanity 😀
TLDR:
cap on the input is bulk storage to amortize bigger load swings
bulk cap on the output (Cout here) helps the regulator cope with same bigger load swings
decoupling caps are near supply pins of digital logic chips to help filter out fast small spikes

Sphere478 wrote on 2022-12-10, 05:23:

all 21 PGA caps have D shaped pads. but they are the same width as the circular pads. we can't bring them closer or it will cut the copper there.

2W 400mA. You can fully ignore 5V on lower part of the board, making proper pads will merely thin the width of traces going to 8 5V pins between M13 and A10
https://www.pcbonline.com/blog/how-to-calcula … -impedance.html

feipoa wrote on 2022-12-10, 08:26:

I am wondering if there is any value in testing sub-100nF caps on a few of the other PGA pins.

imo meh
http://axotron.se/blog/decoupling-primer/ "Impedance vs frequency plots for a few capacitors with different capacitance (1 µF, 100 nF, 10 nF and 1 nF) but same size and therefore same inductance."

Oh that’s a cool chart. Thanks!

Thicker paths also makes resistance lower, which will help with a stable supply. While a smaller path may be sufficient for the current the resistance gives larger swings in voltage with load. (Noise)

This is why my 5500w inverters call for 4/o wiring which is rated to 375?amps. But it is breakered at 175a

Yes, we are likely way over capacitored. But I want to keep them until new design is tested in physical form

This is cool. At this point we are not just making a replica unit but a superior one I think. Fingers crossed for 90mhz!

progress save not a release:

feipoa wrote on 2022-12-10, 05:13:

Maybe U1 and U2 will fit there as well. Only 1 person will ever use those.

Well, that person and everyone else that will put this in an IBM 😉 I didn't check the thread for a few weeks, and I'm thrilled to see the progress you guys are making. Great job on bringing the noise down and getting stable results at 80MHz. I'll try to add the same capacitors around the socket to my hacky thing, see if it makes a difference in stability.

rasz_pl wrote on 2022-12-10, 17:28:

no, and you should snip those legs flush after soldering, they do all act like mini antennas

If looks matter none, I suppose. For a compromise, I think best to snip the legs before soldering them so that solder covers the snip marks.

rasz_pl wrote on 2022-12-10, 17:28:

10 caps on the input is pure insanity :)

I think so too.

rasz_pl wrote on 2022-12-10, 17:28:

...bulk cap on the output (Cout here) helps the regulator cope with same bigger load swings
decoupling caps are near supply pins of digital logic chips to help filter out fast small spikes

Should I check for noise on address and data pins?

Sphere478 wrote on 2022-12-10, 05:23:

all 21 PGA caps have D shaped pads. but they are the same width as the circular pads. we can't bring them closer or it will cut the copper there.

rasz_pl wrote on 2022-12-10, 17:28:

imo meh http://axotron.se/blog/decoupling-primer/ "Impedance vs frequency plots for a few capacitors with different capacitance […]
Show full quote

imo meh
http://axotron.se/blog/decoupling-primer/ "Impedance vs frequency plots for a few capacitors with different capacitance (1 µF, 100 nF, 10 nF and 1 nF) but same size and therefore same inductance."

Nice and concise article with interesting plots. So if we have some noise at 40 MHz that we want to reduce, e.g. download/file.php?id=151551&mode=view , and the other values, for sake of simplicity, are in agreement with the example presented (and we omit PCB impedance) , then 1uF, 100 nF, and 10 nF all meet at the same point (40 MHz) and are already optimised, or lowest impedance, thus lowest noise?

However, the article goes on to discuss validity "up until frequencies where the plane (the PCB, I presume) starts to show its own resonances due to its distributed nature"... "The PCB layout (PCB tracks and vias) can and does add significantly to the total inductance of the capacitor."

When adding in PCB impedance (the article discusses the capacitive component in their model), I noticed the chart appears to shift considerably. So without some computer-aided modelling with the actual layout, it would be hard to know without experimentation what the theoretical best value for decoupling capacitors are. "The PCB layout (PCB tracks and vias) can and does add significantly to the total inductance of the capacitor."

Sphere478 wrote on 2022-12-10, 17:37:

This is cool. At this point we are not just making a replica unit but a superior one I think. Fingers crossed for 90mhz!

I'm pretty sure we are already running into a CPU limitation rather than a PCB limitation and any further revisions are mostly for 'making it the best it can be'. The Evergreen SXL2-66 unit might perform better because it uses a QFP package. Someone here, I think it was user Ph4nt0m, was saying that the QFP package allows for quicker heat dissipation so it has a higher probability to overclock higher. In any case, I am fairly optimistic that we can achieve 90 Mhz with peltier cooling. User pshipkov is more keen on this and has the most experience optimising the condensation factor. I already sent him some PCBs. I also have a bunch of peltiers to run this if there is sufficient interest from others. For my goals, I want heatsink/fan cooling only.

Blavius wrote on 2022-12-10, 19:44:

feipoa wrote on 2022-12-10, 05:13:

Maybe U1 and U2 will fit there as well. Only 1 person will ever use those.

Well, that person and everyone else that will put this in an IBM ;-) I didn't check the thread for a few weeks, and I'm thrilled to see the progress you guys are making. Great job on bringing the noise down and getting stable results at 80MHz. I'll try to add the same capacitors around the socket to my hacky thing, see if it makes a difference in stability.

lol, yes I know. My comment was predicting how many IBM users would use and assemble this in the next few years and I predict 1. If there are more, even better!

feipoa wrote on 2022-12-11, 01:48:

If looks matter none, I suppose. For a compromise, I think best to snip the legs before soldering them so that solder covers the snip marks.

well, maybe not perfectly flush 😀 just close to pcb after soldering. Looking at

you can totally cut 3/4 of sticking out pins, as solder only goes up 1/4.

feipoa wrote on 2022-12-11, 01:48:

Should I check for noise on address and data pins?

You could, but for that you will need really short ground and probing directly at the pins from the bottom of whole motherboard. Mere act of measurement will influence the signal. Looking if there are any visible interferences from other nearby signals, or reflections will be more interesting.
https://edadocs.software.keysight.com/kkbopen … -583415752.html

feipoa wrote on 2022-12-11, 01:48:

Nice and concise article with interesting plots. So if we have some noise at 40 MHz that we want to reduce, e.g. download/file.php?id=151551&mode=view

thats just 2% supply swing, safe to ignore

feipoa wrote on 2022-12-11, 01:48:

and the other values, for sake of simplicity, are in agreement with the example presented (and we omit PCB impedance) , then 1uF, 100 nF, and 10 nF all meet at the same point (40 MHz) and are already optimised, or lowest impedance, thus lowest noise?

Thats how I read it

feipoa wrote on 2022-12-11, 01:48:

However, the article goes on to discuss validity "up until frequencies where the plane (the PCB, I presume) starts to show its own resonances due to its distributed nature"... "The PCB layout (PCB tracks and vias) can and does add significantly to the total inductance of the capacitor."

not if said capacitor sits directly on the pins, at high frequencies currents tend to pick shortest path.

feipoa wrote on 2022-12-11, 01:48:

When adding in PCB impedance (the article discusses the capacitive component in their model), I noticed the chart appears to shift considerably. So without some computer-aided modelling with the actual layout, it would be hard to know without experimentation what the theoretical best value for decoupling capacitors are. "The PCB layout (PCB tracks and vias) can and does add significantly to the total inductance of the capacitor."

VNA - same tool used for optimizing antenna design, because everything is an antenna at high frequencies 😀 https://www.signalintegrityjournal.com/blogs/ … edance-analysis From my point of view people doing this kind of work wear wizard robes, remember https://archive.org/details/highspeeddigital0000john/ ? its right in the title 😀

if you cut them prior to soldering like feipoa suggested you can get them almost completely flush, there is really no downside

maxtherabbit wrote on 2022-12-11, 02:59:

if you cut them prior to soldering like feipoa suggested you can get them almost completely flush, there is really no downside

Trouble soldering properly is the downside. Solder needs surface to adhere. Of course you could count on tight hole (shut up) doing all the work here, but thats just asking for trouble. There are special press fit pins that can do that (aerospace, cars):
- used for superior long term mechanical reliability
- more expensive
- good luck finding PGA132 with press fit pins
- they also need to stick out, and you cant cut the sticking out part

rasz_pl wrote on 2022-12-11, 03:05:

maxtherabbit wrote on 2022-12-11, 02:59:

if you cut them prior to soldering like feipoa suggested you can get them almost completely flush, there is really no downside

Trouble soldering properly is the downside. Solder needs surface to adhere.

it's not a problem, I've done it many times

you heat the pad, then flood it while keeping heat applied - the solder naturally fills the PTH

When I have cut leads flush with the PCB, I noticed it is a bit more difficult for solder to fill the via. I feel like it balls on the surface more than flowing into the via. I don't fully understand the mechanics behind it, but I suspect it has to do with the iron tip not quite touching both the via and the lead simultaneously.

Rasz_pl, your passion for electronics is impressive. Having 3 kids killed it for me. As the years go on, the more I forget, and the more I forget what I forgot. That VNA antenna link you listed reminded me I once had a graduate lab course which addressed this topic, but all knowledge has since been flushed clean.

Before wrapping up, I wanted to look a little more into this low freq. noise, so I swapped from 1x to 10x probes and set the scope for 10x. First I ran a quick comparison with CH1 on 10x probe and CH2 on 1x probe. I also told the scope's firmware what attenuation probe is on each channel.

Yellow is Vout from regulator w/10x probe. Blue is Vout from regulator w/1x probe. Why the 3-4x discrepency in Vpp measurements? I figured at most 50% error due to different precision.

Shows around 5 Khz this time. Hmm. Curiously it is twice that of 2.5 KHz measured previously on this motherboard:

CH1-Yellow stays Vout on the iterposer for all these images. GND is used at interposer. Then setup CH2-blue to be 10x and set measure Vcc5 on interposer. Waveform still present on 5V:

Next I take Vcc5's ground away from the interposer and connect it to molex GND. The waveform blurrs considerably:

Now I take Vcc5 measurement from the BIOS EEPROM chip instead of the interposer, but still use the GND on the interposer. Waveform still present:

Next I keep CH2-blue at EEPROM 5V but move the GND to the molex. Waveform blurs considerably:

Finally, I leave CH1-yellow on Vcc3 but I move its GND away from interposer and onto molex GND. Using GND on molex blurs the waveform. Is there some kind of ground loop oscillations occurring between the interposer's GND planes?

feipoa wrote on 2022-12-11, 13:25:

Before wrapping up, I wanted to look a little more into this low freq. noise, so I swapped from 1x to 10x probes and set the scope for 10x.

you should have been using 10x all along 😐 10x is not only signal divided by 10, but more importantly impedance multiplied by 10

feipoa wrote on 2022-12-11, 13:25:

Yellow is Vout from regulator w/10x probe. Blue is Vout from regulator w/1x probe. Why the 3-4x discrepency in Vpp measurements? I figured at most 50% error due to different precision.
Shows around 5 Khz this time. Hmm. Curiously it is twice that of 2.5 KHz measured previously on this motherboard:

impedance, plus from previous pictures you keep clipping ground on long leads making measurement unrepresentative

feipoa wrote on 2022-12-11, 13:25:

ground away from the interposer and connect it to molex GND

like that

feipoa wrote on 2022-12-11, 13:25:

Finally, I leave CH1-yellow on Vcc3 but I move its GND away from interposer and onto molex GND. Using GND on molex blurs the waveform. Is there some kind of ground loop oscillations occurring between the interposer's GND planes?

User error, most likely you are inducing phantom noise into the system by using scope wrong. You might be seeing aliasing, or picking up nearby radio station 😀
Tutorial https://www.youtube.com/watch?v=9GqfZMcrAFY

Is 1 M-ohm input impedance not sufficient for these measurements?

This is the interposer GND I've been using for the last little while and with these tests. It is as short as I could make it. Clipping two probe GNDs directly to the header was causing shorts with the adjacent 5V pin, so I had to use a connector:

I don't think I'm picking up a radio station because when I use a much longer GND to the molex, the waveform disappears/blurs: