GigAHerZ wrote on 2022-01-31, 12:44:

Yes. I've played around with this beauty: QDI V4S471/G locks up with 1024kB of cache [Fixed! Nicer Award BIOS available!] And "T […]
Show full quote

DonutKing wrote on 2022-01-31, 11:54:

-I find that the BIOS setting 'Local Bus Ready' is somewhat unstable when set to 'Transparent'; I have to set to 'Synchronize' for best stability. Transparent mode gives a small performance boost in benchmarks. Other people have the same experience?

Yes. I've played around with this beauty: QDI V4S471/G locks up with 1024kB of cache [Fixed! Nicer Award BIOS available!]
And "Transparent" did give a bit better memory throughput on VLB videocard in speedsys.
NB! You may want to try that bios from that thread as well. All bioses are really the same if chipset is same. Only options that are visible are different. (And, theoretically, newer dated bios may have something for the chipset, too, but i don't have the capabilities to go that deep...)

Thanks, I might try that BIOS over the weekend.

I flashed the official 0402.001 BIOS and I'm still getting the same sound issues as I was with the version in this thread.... so I fear the BIOS isn't to blame, perhaps my board has a fault or its just too much for a rev 1.7 to handle.

DonutKing wrote on 2022-01-31, 11:54:

I was running the BIOS version linked in this thread but I found that with L1 WB enabled I was getting choppy digital audio, and also some intermittent issues with my floppy drive - I could copy files off it but straight after I would get strange characters in DIR A: output. Presumably there are some DMA issues.

This is also an issue with this BIOS and L1 WB enables and the Cyrix 5x86. It was reported by another user here and I can confirm I experienced the same issue. So it appears as though it affects AMD 586 CPUs as well.

Now we know why Asus disabled it.

Your problems with the floppy and the sound card sound like a DMA problem. The L1 of the Am5x86 supports Write Back Mode, i.e. it only writes to RAM when the corresponding memory addresses have changed. If the memory addresses are changed at the same time by another component via Direct Memory Access (DMA) without the TAG registers of the cache noticing this, there are inconsistencies in the memory and the system no longer runs smoothly. Floppies are addressed via DMA and SCSI controllers via bus mastering as well. A cascaded cache with L1+L2 in WB makes things even more complicated.

The SV2GX4 has its problems with L1WB, but not with all CPUs. For example, in my Rev. 2.1 board, the Am5x86, the AMD DX4 SV8B, the Intel DX2WB and the Intel DX4 run with L1WB without DMA problems. With the Cx5x86 there are partly problems and with the POD the DMA with L1WB is not possible at all. I have already played with all documented registers, but failed. Very sad, because with the POD@100MHz the board is faster than a real Pentium 100 with Neptune chipset.

DonutKing wrote on 2022-01-31, 11:54:

Hello, sorry to necro an old thread. I've got a VL/i486SV2 rev 1.7 modded to GX4 using this guide Specs: Am5x86-133 16MB single […]
Show full quote

Hello, sorry to necro an old thread.
I've got a VL/i486SV2 rev 1.7 modded to GX4 using this guide
Specs:
Am5x86-133
16MB single 60ns SIMM
1024kb L2 cache using a 128kx8 for TAG
VLB ET4000w32/p 2MB
VLB Promise EIDE2000 I/O Controller
AWE64 Gold
Gravis Ultrasound Classic
2GB CF card HDD
Sony CDU55E CDROM

I was running the BIOS version linked in this thread but I found that with L1 WB enabled I was getting choppy digital audio, and also some intermittent issues with my floppy drive - I could copy files off it but straight after I would get strange characters in DIR A: output. Presumably there are some DMA issues.

I found that disabling the L1 WB by removing the orange jumpers in the document in the link above fixed my sound issues.
Alternatively, installing a DX4 Overdrive which doesn't support L1 WB mode did not exhibit the issue.

Has anyone had similar issues with a REV1.7 board?
Perhaps BIOS version 0402.001 is not 100% compatible with this version of the board?

Some other questions:
-does anyone know what JP24 does on this board? it is unmarked on my board, and it doesn't seem to match up with any of the manuals I find online. ON my board it is a single jumper near the edge, the manuals usually show it as a group of 3 jumpers for setting the bus speed.
-I find that the BIOS setting 'Local Bus Ready' is somewhat unstable when set to 'Transparent'; I have to set to 'Synchronize' for best stability. Transparent mode gives a small performance boost in benchmarks. Other people have the same experience?

Latest BIOS should work fine (if possible get the version modded to enable dirty tag bit for L2 WB). I think the jumpers for setting L1 WB in that thread are not entirely correct, please follow my guide, those jumpers should be the same on 1.7 and 1.8:

• JP16 pins 1-2 (this connects the WB/WT# pin of the CPU to a pull-up resistor)
• JP17 pins 2-3 (this connects the W/R# output to the INV input of the CPU)
• JP18 pins 2-3 (this connects the HITM# input of the chipset to the HITM# output of the CPU)
• Finally, set both JP5 and JP6 to 1-2 for the proper L1 WB trap setting of the chipset

I also suggest to set the power management jumpers: JP16 3-4 (SRESET) and 5-6 (SMI ACT), as well as JP18 4-5 (SMI)

Also, I've found out that even though I can set the tightest timings with a DX4-100 or AMD 5x86-133, I need to disable the "DRAM Write Burst" option in the BIOS when using L1 WB or there will be instabilities. You may want to check that.

- Regarding JP24, I need to check the manual as I don't remember, will reply again when I have the info
- The "Synchronize" vs "Transparent" seems to depend on the video card in my experience. For example, my S3 Trio64 works fine and gets a small performance increase with "Transparent", while an ET4000/W32P seems to work and gets the performance increase but some games fail to load (for example Rise of the Triad). So it seems to be a trial and error process which requires some extensive testing (not sure if the additional performance is worth it)

PC-Engineer wrote on 2022-01-31, 14:21:

The SV2GX4 has its problems with L1WB, but not with all CPUs. For example, in my Rev. 2.1 board, the Am5x86, the AMD DX4 SV8B, the Intel DX2WB and the Intel DX4 run with L1WB without DMA problems. With the Cx5x86 there are partly problems and with the POD the DMA with L1WB is not possible at all. I have already played with all documented registers, but failed. Very sad, because with the POD@100MHz the board is faster than a real Pentium 100 with Neptune chipset.

The POD unfortunately doesn't seem to work properly with versions < 2.0 of this board... I couldn't find any combination where it was stable, even with L1 set to WT.

The versions below 2.0 have the write back pin to the POD hard wired. It is not possible to switch the POD to L1WT with this versions.

TheMobRules wrote on 2022-01-31, 15:23:

Latest BIOS should work fine (if possible get the version modded to enable dirty tag bit for L2 WB). I think the jumpers for set […]
Show full quote

Latest BIOS should work fine (if possible get the version modded to enable dirty tag bit for L2 WB). I think the jumpers for setting L1 WB in that thread are not entirely correct, please follow my guide, those jumpers should be the same on 1.7 and 1.8:

• JP16 pins 1-2 (this connects the WB/WT# pin of the CPU to a pull-up resistor)
• JP17 pins 2-3 (this connects the W/R# output to the INV input of the CPU)
• JP18 pins 2-3 (this connects the HITM# input of the chipset to the HITM# output of the CPU)
• Finally, set both JP5 and JP6 to 1-2 for the proper L1 WB trap setting of the chipset

I also suggest to set the power management jumpers: JP16 3-4 (SRESET) and 5-6 (SMI ACT), as well as JP18 4-5 (SMI)

Also, I've found out that even though I can set the tightest timings with a DX4-100 or AMD 5x86-133, I need to disable the "DRAM Write Burst" option in the BIOS when using L1 WB or there will be instabilities. You may want to check that.

- Regarding JP24, I need to check the manual as I don't remember, will reply again when I have the info
- The "Synchronize" vs "Transparent" seems to depend on the video card in my experience. For example, my S3 Trio64 works fine and gets a small performance increase with "Transparent", while an ET4000/W32P seems to work and gets the performance increase but some games fail to load (for example Rise of the Triad). So it seems to be a trial and error process which requires some extensive testing (not sure if the additional performance is worth it)

Thanks for this info.
Unfortunately trying different jumpers didn't lead to any success.

I managed to get the CPU detected correctly as a 5x86-133-P75 with the following jumpers:

• JP16 pins 1-2
• JP17 pins 2-3 and 5-6 (without 5-6, it detected as a 100MHz Enhanced Am486)
• JP18 pins 2-3
• JP19 pins 1-2
• JP20 pins 2-3
• JP5 pins 1-2
• JP6 pins 2-3

However, I still had the choppy audio issues. Removing JP16 fixed it. so presumably my board won't behave with WB L1 cache.

Your guide suggested setting JP6 to 1-2 however this caused the system to hang on boot just after the System Configuration table, and wouldn't proceed to boot DOS. This was similar behaviour to setting JP20 to 1-2

I confirmed this with two different REV1.7 boards - same behaviour. I also tried the official 0402.001 BIOS and the modded 0402.002 BIOS posted earlier in this thread with no difference.

DonutKing wrote on 2022-02-01, 03:35:

without 5-6, it detected as a 100MHz Enhanced Am486

Yes, I failed to mention this in my previous post, but that jumper sets the DX4 multiplier to 2x, which is actually 4x for the 5x86 so that is indeed the proper way to get 133MHz.

DonutKing wrote on 2022-02-01, 03:35:

Your guide suggested setting JP6 to 1-2 however this caused the system to hang on boot just after the System Configuration table, and wouldn't proceed to boot DOS. This was similar behaviour to setting JP20 to 1-2

Did you try keeping JP6 set to 1-2 (but JP20 to 2-3) and disabling DRAM Write Burst as I suggested? In my case it also hangs after the config table if I don't disable that option in the BIOS. On the other hand setting JP20 to 1-2 in order to connect the CACHE# line to the chipset always locks up the computer, but apparently that line is not really needed for some chipsets (at least according to J. Steunebrink). Without JP6 however I'm afraid the chipset won't be able to properly work with L1 WB unfortunately.

L1 WB is a big mess on most pre-1995 motherboards, I wonder why the manufacturers had so much trouble with the implementation. Same with the dirty tag bit bullshit on SiS471 based boards. I know the incompatibilities with the POD are due to a last minute change in the specs by Intel, but not sure about L1 WB on 486 chips.

TheMobRules wrote on 2022-02-01, 04:10:

Did you try keeping JP6 set to 1-2 (but JP20 to 2-3) and disabling DRAM Write Burst as I suggested? In my case it also hangs after the config table if I don't disable that option in the BIOS. On the other hand setting JP20 to 1-2 in order to connect the CACHE# line to the chipset always locks up the computer, but apparently that line is not really needed for some chipsets (at least according to J. Steunebrink). Without JP6 however I'm afraid the chipset won't be able to properly work with L1 WB unfortunately.

Yes, disabling DRAM Write Burst allows the system to boot but the choppy audio still remains.

Edit to add - these are the games I've noticed audio issues in so far:
Mystic Towers
Hocus Pocus - Gravis Ultrasound also sounds terrible when L1WB is enabled
Rise of the Triad - hard to notice in gameplay, but when you quit the game it will play a longer sound clip like a car crashing etc, this is quite choppy.

All sound fine when L1 cache is running in WT mode.

Tried a few others and didn't seem to notice the issue - doom, hexen, jazz jackrabbit, raptor. No issues with digital audio in windows 3.11 either.

PC-Engineer wrote on 2022-01-31, 15:33:

The versions below 2.0 have the write back pin to the POD hard wired. It is not possible to switch the POD to L1WT with this versions.

Hello,

sorry to re-open this one year later .....
What does that mean exactly?

I am asking because I try to enable L1WB on an Asus VL/I-486SVGOX4 Rev.1.2
I tried settings for "P24T" and "P24CT".
Re: 2 questions about Asus VL/I-486SV2GX4

I had measured in Rev. 1.7 - there was Pin T1 permanent set to WB (only for P24T), without any possibility to set it via Jumper.

https://x86.fr/experimental-pentium-overdrive … g-with-the-uca/
http://www.dickhardtstrasse.org/Hardwarehandb … ml?cpu_486.html
http://ps-2.kev009.com/eprmhtml/eprmx/h12203.htm

PC-Engineer wrote on 2023-01-02, 21:27:

I had measured in Rev. 1.7 - there was Pin T1 permanent set to WB (only for P24T), without any possibility to set it via Jumper. […]
Show full quote

I had measured in Rev. 1.7 - there was Pin T1 permanent set to WB (only for P24T), without any possibility to set it via Jumper.

https://x86.fr/experimental-pentium-overdrive … g-with-the-uca/
http://www.dickhardtstrasse.org/Hardwarehandb … ml?cpu_486.html
http://ps-2.kev009.com/eprmhtml/eprmx/h12203.htm

Oh. So for P24T the WB/WT pin is in the "outer zone" that a normal 486 does not have?

Normal for insufficient rows addressing to support all double sided simms in all slots.

Same situation with intel boards all eras cannot go beyond 2 ranks per DIMM. Requires buffered DIMMs to handle 4 ranks or more on supported CPUs especially Intel E5 xeon or up.
Same with threadrippers too.

Cheers,

CoffeeOne wrote on 2023-01-02, 23:13:

PC-Engineer wrote on 2023-01-02, 21:27:

I had measured in Rev. 1.7 - there was Pin T1 permanent set to WB (only for P24T), without any possibility to set it via Jumper. […]
Show full quote

I had measured in Rev. 1.7 - there was Pin T1 permanent set to WB (only for P24T), without any possibility to set it via Jumper.

https://x86.fr/experimental-pentium-overdrive … g-with-the-uca/
http://www.dickhardtstrasse.org/Hardwarehandb … ml?cpu_486.html
http://ps-2.kev009.com/eprmhtml/eprmx/h12203.htm

Oh. So for P24T the WB/WT pin is in the "outer zone" that a normal 486 does not have?

Yes

Re: Socket 1/2/3 Voltage Interposer Tweaker (Alpha, seeking testers)

for issues setting the mode via hardware my device has you covered.

earlier it was mentioned as impossible, this may make it possible.

PC-Engineer wrote on 2023-01-03, 06:20:

Yes

Hi,

Can you confirm (found it in a message from pshipkov)
.... pin B13, connected to +5V -> L1 WB enabled.

Is that all is needed for Am5x86 setting L1 to WB?

CoffeeOne wrote on 2023-01-03, 10:36:

Can you confirm (found it in a message from pshipkov)
.... pin B13, connected to +5V -> L1 WB enabled.

Is that all is needed for Am5x86 setting L1 to WB?

There are three things you need to get a properly working L1 WB system.

• The signalling between the chipset and the processor needs to provide the L1WB signals. L1WB uses different pins for early Cyrix processors and Intel DX4/AMD processors. Usually there are some jumpers to select the WB pinout. While the Pentium Overdrive uses a third set of pins for L1WB signalling, the Pentium Overdrive has those signals on the extra outer row of pins, so they can be connected straight to either the Cyrix or the Intel DX4 pins. On the VL/I-486SV2GX4, this is accomplished by setting JP16 3-4 (for SRESET), JP17 2-3 (for INV) and JP18 2-3 (for HITM). SRESET is not "just nice to have", but necessary in some corner case: 286-class protected mode software that does not support the 386 way to leave protected mode uses the keyboard controller to send a reset signal to the CPU, so it re-enters real mode. When the reset signal from the keyboard controller is routed to the RESET (instead of the new SRESET) pin of the CPU, this operation clear the complete L1 cache, without writing it back to RAM. As long as you operate the system in L1WT mode, the only consequence is the performance impact caused by the cache flush. But in L1WB mode, you lose all unwritten write-back data in the L1 cache. On the other hand, SRESET ("soft reset") does not clear the L1 cache and can be used safely with better performance in both L1WT and L1WB mode.
• The chipset needs to support L1WB operation, and needs to be configured to use it. When DMA cycles occur, the chipset needs to ask the processor whether it still has unwritten data for that address in L1WB, and if so, wait for the processor to flush L1 to L2 and/or main memory before the DMA cycle actually happens. On many systems, chipset setup is performed by the BIOS, which configures the chip according to the CPUID of the current processor. This only works if the BIOS recognizes the CPUID to select between "L1WT", "L1WB in Cyrix mode" and "L1WB in Intel/AMD mode". As the 5x86 uses a different CPUID in x4 mode than it uses in DX4-compatible x3 mode, older BIOSes might not correctly configure the chipset for the 5x86 in x4 mode. On the VL/I-486SV2GX4, the chipset is configured using JP5/JP6 instead of the BIOS, if I understand this thread correctly.
• The processor needs to be configured to operate in L1WB mode. For AMD 5x86, DX4 SV8B and Intel enhanced DX4 processors, this is indeed accomplished by pulling pin B13 high. On the VL/I-486SV2GX4, this can be enabled by setting JP16 1-2. For Cyrix processors (both the "Cyrix pinout" processors and the "Standard pinout" processors), L1WT/L1WB is under BIOS control, and not configurable via any jumpers. If the BIOS contains a "L1 mode" option, that option is used to configure Cyrix processors only and ignored for Intel and AMD processors.

Just pulling B13 high without ensuring proper signal routing and chipset configuration will inevitably cause the DMA issues mentioned in this thread (bad soundblaster voice playback, floppy problems).

PC-Engineer wrote on 2023-01-02, 21:27:

http://ps-2.kev009.com/eprmhtml/eprmx/h12203.htm

That's a very convenient source comparing all the 486 pinouts out there. I really like the table on that page. But like with most good things, there is a catch: Don't trust this web site to be accurate on the pins that do not differ between the different 486 processors. The pinout picture on that page has A13 and A16 swapped.

mkarcher wrote on 2023-01-03, 11:39:

PC-Engineer wrote on 2023-01-02, 21:27:

http://ps-2.kev009.com/eprmhtml/eprmx/h12203.htm

That's a very convenient source comparing all the 486 pinouts out there. I really like the table on that page. But like with most good things, there is a catch: Don't trust this web site to be accurate on the pins that do not differ between the different 486 processors. The pinout picture on that page has A13 and A16 swapped.

Hi, thx for the info. I doubt it will help me 😁

I just played around with the board (svgox4 rev.1.2)
and found out with checking for connection:
JP 22 pin 5 is connected to HTM (CPU A12)
JP 9 Pin 1 is connected to INV (CPU A10) => That is labelled with Cyrix/Intel, so Pin 1 would choose a Cyrix setting.

I did not find any connections from a jumper to neither CACHE (CPU B12) nor to WB/WT (CPU B13)

mkarcher wrote on 2023-01-03, 11:19:

There are three things you need to get a properly working L1 WB system. […]
Show full quote

CoffeeOne wrote on 2023-01-03, 10:36:

Can you confirm (found it in a message from pshipkov)
.... pin B13, connected to +5V -> L1 WB enabled.

Is that all is needed for Am5x86 setting L1 to WB?

There are three things you need to get a properly working L1 WB system.

• The signalling between the chipset and the processor needs to provide the L1WB signals. L1WB uses different pins for early Cyrix processors and Intel DX4/AMD processors. Usually there are some jumpers to select the WB pinout. While the Pentium Overdrive uses a third set of pins for L1WB signalling, the Pentium Overdrive has those signals on the extra outer row of pins, so they can be connected straight to either the Cyrix or the Intel DX4 pins. On the VL/I-486SV2GX4, this is accomplished by setting JP16 3-4 (for SRESET), JP17 2-3 (for INV) and JP18 2-3 (for HITM). SRESET is not "just nice to have", but necessary in some corner case: 286-class protected mode software that does not support the 386 way to leave protected mode uses the keyboard controller to send a reset signal to the CPU, so it re-enters real mode. When the reset signal from the keyboard controller is routed to the RESET (instead of the new SRESET) pin of the CPU, this operation clear the complete L1 cache, without writing it back to RAM. As long as you operate the system in L1WT mode, the only consequence is the performance impact caused by the cache flush. But in L1WB mode, you lose all unwritten write-back data in the L1 cache. On the other hand, SRESET ("soft reset") does not clear the L1 cache and can be used safely with better performance in both L1WT and L1WB mode.
• The chipset needs to support L1WB operation, and needs to be configured to use it. When DMA cycles occur, the chipset needs to ask the processor whether it still has unwritten data for that address in L1WB, and if so, wait for the processor to flush L1 to L2 and/or main memory before the DMA cycle actually happens. On many systems, chipset setup is performed by the BIOS, which configures the chip according to the CPUID of the current processor. This only works if the BIOS recognizes the CPUID to select between "L1WT", "L1WB in Cyrix mode" and "L1WB in Intel/AMD mode". As the 5x86 uses a different CPUID in x4 mode than it uses in DX4-compatible x3 mode, older BIOSes might not correctly configure the chipset for the 5x86 in x4 mode. On the VL/I-486SV2GX4, the chipset is configured using JP5/JP6 instead of the BIOS, if I understand this thread correctly.
• The processor needs to be configured to operate in L1WB mode. For AMD 5x86, DX4 SV8B and Intel enhanced DX4 processors, this is indeed accomplished by pulling pin B13 high. On the VL/I-486SV2GX4, this can be enabled by setting JP16 1-2. For Cyrix processors (both the "Cyrix pinout" processors and the "Standard pinout" processors), L1WT/L1WB is under BIOS control, and not configurable via any jumpers. If the BIOS contains a "L1 mode" option, that option is used to configure Cyrix processors only and ignored for Intel and AMD processors.

Just pulling B13 high without ensuring proper signal routing and chipset configuration will inevitably cause the DMA issues mentioned in this thread (bad soundblaster voice playback, floppy problems).

Hello,

I now think I have a chance to make it working:
1)
SRESET is a setting in common with Intel SL CPUs, INV and HTM I can maybe set with jumpers

EDIT: A12 means SMI on Cyrix 486! not HTM
so probably this Cyrix jumper does NOT the right thing......

2) chipset to WB => should be JP7, and JP8 on this revision, see my picture.

3)
pull WB/WT high, seems for this I need a wire ....

CoffeeOne wrote on 2023-01-03, 11:58:

I did not find any connections from a jumper to neither CACHE (CPU B12) nor to WB/WT (CPU B13)

This seems to indicate that this board revision does not support the DX4/5x86 L1WB pinout. This is quite common for earlier 486 boards, as this is the latest of three different WB pinouts to appear. Cyrix was the first company to have a 486 processor with L1WB: In fact all Cyrix 486 processors for a 486 socket do support L1WB if the mainboard/chipset cooperates. Intel later specified the PODP with all its extra control pins on the outer row of pins. The normal Intel/AMD DX2 and DX4 processors at that time were L1WT only. The "standard pinout" (as Cyrix called it later) has been established when Intel introduced the &EW version of the 486DX4 with L1WB support, and the AMD DX4 SV8B, AMD 5x86, Cx486DX4 and Cx5x86 followed the Intel enhanced DX4 pinout.

AFAIK the protocol of the PODP and the enhanced DX4 processor are identical, but the Cyrix protocol is slightly different. I might mix it up with the SMM protocol, though. I know for sure that the Cyrix and Intel SMM protocols are not compatible. As it seems your board is not prepared for the DX4 WB pinout, it still might be prepared for the PODP pinout. It's possible to rework a board to connect the PODP cache control pins to the corresponding DX4 cache control pins, but make sure you remove any jumpers / cut traces that connect the DX4 pins with incompatible Cyrix-specific signals. After that rework, the PODP jumper setting should work with 5x86 processors, too.