Reply 60 of 287, by jakethompson1
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mkarcher wrote on 2023-04-25, 20:36:jakethompson1 wrote on 2023-04-25, 20:27:The read ahead mode is the Achilles heel of the infamous CMD640/RZ1000, right?
Yes. Those chips used a single FIFO (possibly just 2 words) for read-ahead for both IDE channels. This means that in the case of an IDE data transfer on the primary channel getting interrupted by a different task that tries to issue a command on the second channel will mess up the FIFO state. Do you remember the generic Windows 95 PCI IDE driver calling the the supported PCI IDE interface chips "dual FIFO"? This basically means: "Not like the CMD640/RZ1000". The usual workarounds to deal with the CMD640 or RZ1000 chips was to either make sure that only one IDE channel is ever in use at the same time, or possibly just making sure an REP INSW/INSD not getting interrupted.
Do you think those problems (since Intel got burned by those on their own boards using those chips) played any role in Intel developing the PIIX as the "IDE chip to end all other IDE chips" or would it have already been well under development by the time those issues surfaced?
It does seem that it puts all the PCI/VLB IDE chips that came before it to shame and in particular erodes any performance advantage of SCSI over IDE once bus mastering is working and the OS takes advantage of it, right?