My board is revision 1.8 and it doesn't have any silkscreen or stickers indicating how 50 MHz jumpers would set. I have run all possible jumper combinations for JP25, 26, 27, 28. I measured CLK directly at the CPU's CLK pin, I measured PCI CLK from the PCI slot. The results are attached.
The attachment Asus_PVI_486SP3_complete_clk_gen_table.JPG is no longer available
The entries I highlighted in yellow are the ones which I believe are the correct and operational. All others are, non-functional, except for a second 25 MHz setting with a bumpy waveform.
The theory that the VIA PLL follows the convention of the AV9155 PLL seems sound, however the measured results don't follow this CLK*2 convention. The exception is for the 50 MHz setting, which on my board is:
50 MHz FSB
JP25, JP26, JP27, JP28
1-2, 1-2, 2-3, 1-2
If we adjust JP25 to 2-3, we'd expect the 50 MHz setting to double, which it does, but only for the 50 MHz setting.
Thus,
JP25, JP26, JP27, JP28
2-3, 1-2, 2-3, 1-2
has the following waveform, but is NO POST:
Yellow is CPUCLK, blue is PCI CLK.
The attachment 100MHz.JPG is no longer available
From this analogy, we might expect the 33 MHz setting, with JP25 set to 2-3 to be the 66 MHz setting, but alas, it is not. It is still 33 MHz and no POST. For the most part, when JP25 is set to 2-3, the PCI CLK and CPU CLK are 180 degrees out of phase. All but one setting with JP25 set to 2-3 would not POST (the other being the second 25 Mhz FSB setting with bumpy waveform).
Plan your life wisely, you'll be dead before you know it.