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VIAFSB - DOS FSB utility for VIA chipsets

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Reply 80 of 91, by enaiel

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Bruno128 wrote on 2024-08-01, 21:41:

It's nice to see you back
Testing version 0.3.0 with W83194BR-39B / SL-65FVB

Also tried other values nothing happens.

Thanks for testing!

That's very weird that it is reading the FSB all wrong. Are you sure you have the right PLL?

#1 VIA C3 Ezra-T 1.0GHz / MSI MS-6368 / Voodoo2+ViRGE GX / SBPro2+YMF744+AWE64+SC-7
#2 Pentium III-S Tualatin 1.40GHz / QDI A10T / Voodoo3 3000+GF4 Ti4200 / Audigy+AU8830+SC-50

Reply 82 of 91, by enaiel

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Bruno128 wrote on 2024-08-01, 23:03:

Ah, unfortunately you can't go by specifications. Often different revisions of the same motherboard use different PLL chips. You need to visually identify the PLL chip on your motherboard to be absolutely sure.

#1 VIA C3 Ezra-T 1.0GHz / MSI MS-6368 / Voodoo2+ViRGE GX / SBPro2+YMF744+AWE64+SC-7
#2 Pentium III-S Tualatin 1.40GHz / QDI A10T / Voodoo3 3000+GF4 Ti4200 / Audigy+AU8830+SC-50

Reply 83 of 91, by Bruno128

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enaiel wrote on 2024-08-01, 23:40:
Bruno128 wrote on 2024-08-01, 23:03:

Ah, unfortunately you can't go by specifications. Often different revisions of the same motherboard use different PLL chips. You need to visually identify the PLL chip on your motherboard to be absolutely sure.

I’m saying it’s literally this one on the photo.

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Reply 84 of 91, by enaiel

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Bruno128 wrote on 2024-08-02, 07:04:

I’m saying it’s literally this one on the photo.

Oh, okay. In that case, could you run the dump command and send me the output? It will not actually change the frequency but just do a dry run.

VIAFSB W83194BR-39B 66.82/33.41 -d > dump.txt

#1 VIA C3 Ezra-T 1.0GHz / MSI MS-6368 / Voodoo2+ViRGE GX / SBPro2+YMF744+AWE64+SC-7
#2 Pentium III-S Tualatin 1.40GHz / QDI A10T / Voodoo3 3000+GF4 Ti4200 / Audigy+AU8830+SC-50

Reply 85 of 91, by Bruno128

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enaiel wrote on 2024-08-02, 11:42:

VIAFSB W83194BR-39B 66.82/33.41 -d > dump.txt

VIAFSB v0.3.0 - DOS FSB utility for VIA chipsets.
VIAFSB: Trying to set FSB to 66.82/33.41 using PLL W83194BR-39B...
VIAFSB: Found supported VIA Southbridge: VT82C596/A
VIAFSB: Using SMBus Config Address: 0x90
VIAFSB: Found SMBus Address: 0x5001
VIAFSB: Using instead SMBus Address: 0x5000
VIAFSB: SMBus is enabled
VIAFSB: VIA Southbridge Revision ID: 0x00
VIAFSB: Using PLL W83194BR-39B...
VIAFSB: PLL W83194BR-39B is supported
VIAFSB: Found PLL at SMBus Slave Address: 0x69
W83194BR-39B: Read 13 bytes (hex): 00 CF FF FF 87 F3 00 B0 27 00 97 62 51
W83194BR-39B: FSB_BYTE(0) read (hex bin): 00 00000000
W83194BR-39B: FS_SEL_BIT(1) is NOT set in FSB_BYTE(0). Getting FSB from Latches...
W83194BR-39B: FS5 FS4 FS3 FS2 FS1 FS0 (bits): 0 0 0 0 0 0
W83194BR-39B: Got key for (0 0 0 0 0 0) (hex bin): 00 00000
VIAFSB: Got FSB from PLL W83194BR-39B: 80.00/40.00
VIAFSB: Requested FSB 66.82/33.41 is supported by PLL W83194BR-39B (PCI divider 2)
W83194BR-39B: Found key for FSB(66.82/33.41) (hex bin): 03 00011
W83194BR-39B: FS5 FS4 FS3 FS2 FS1 FS0 (bits): 0 0 0 0 1 1
W83194BR-39B: Writing FSB_BYTE(0) (hex bin): 0E 00001110
W83194BR-39B: Writing 13 bytes (hex): 0E CF FF FF 87 F3 00 B0 27 00 97 62 51
VIAFSB: Unable to set FSB 66.82/33.41 using PLL W83194BR-39B

And I also would like to make a request for another PLL ready for testing, ICS 94228 datasheet

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Reply 86 of 91, by Bruno128

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Testing version 0.3.0 with ICS950405AF / Asus K8V SE Deluxe
Dump looks like this, in reality it halts/freezes the system.

VIAFSB v0.3.0 - DOS FSB utility for VIA chipsets.
VIAFSB: Trying to set FSB to 180.00/0.00 using PLL ICS950405...
VIAFSB: Found supported VIA Southbridge: VT8237/R
VIAFSB: Using SMBus Config Address: 0xD0
VIAFSB: Found SMBus Address: 0x0401
VIAFSB: Using instead SMBus Address: 0x0400
VIAFSB: SMBus is enabled
VIAFSB: VIA Southbridge Revision ID: 0x00
VIAFSB: Using PLL ICS950405...
VIAFSB: PLL ICS950405 is supported
VIAFSB: Found PLL at SMBus Slave Address: 0x69
ICS950405: Read 24 bytes (hex): F7 FF FF F5 7F 7F 18 01 CC 77 80 E2 E7 06 18 00 F7 FF FF F5 7F 7F 18 01
ICS950405: FSB_BYTE(0) read (hex bin): F7 11110111
ICS950405: FS_SEL_BIT(-1) is NOT set in FSB_BYTE(0). Getting FSB from Latches...
ICS950405: FS5 FS4 FS3 FS2 FS1 FS0 (bits): 0 0 0 1 1 1
ICS950405: Got key for (0 0 0 1 1 1) (hex bin): 07 00111
VIAFSB: Got FSB from PLL ICS950405: 200.40/33.40
VIAFSB: Requested FSB 180.00/30.00 is supported by PLL ICS950405 (PCI divider 6)
ICS950405: Writing BYTE_COUNT_BYTE(6) (hex bin): 0F 00001111
ICS950405: Writing 15 bytes (hex): F7 FF FF F5 7F 7F 0F 01 CC 77 80 E2 E7 06 18
ICS950405: Read 24 bytes (hex): F7 FF FF F5 7F 7F 18 01 CC 77 80 E2 E7 06 18 00 F7 FF FF F5 7F 7F 18 01
ICS950405: Found key for FSB(180.00/30.00) (hex bin): 09 01001
ICS950405: FS5 FS4 FS3 FS2 FS1 FS0 (bits): 0 0 1 0 0 1
ICS950405: Writing FSB_BYTE(0) (hex bin): F9 11111001
ICS950405: Writing 15 bytes (hex): F9 FF FF F5 7F 7F 18 01 CC 77 80 E2 E7 06 18
VIAFSB: Unable to set FSB 180.00/30.00 using PLL ICS950405

This is the detection although the frequency options are a bit weird and none of them work

The attachment viafsb030-ics950405 detection.jpg is no longer available

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Reply 87 of 91, by dj_pirtu

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Works fluently with Asus A7V133-VM! ICS94215.

Reply 90 of 91, by Fiergo

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Regarding above VIA VP3 motherboard, it's VT82C586B based.
I've implemented some code on my own by using PLL ICS9148BF-04 datasheet and app reported that SMBus is just disabled and it failed to enable it.
I confirm that doesn't work in such early VIA motherboard.

Reply 91 of 91, by Danger Manfred

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Amazing tool, could you try to add support for the Epox/ProNix EP-8KTA3+?

The southbridge is a VIA VT82C686B, and the PLL is this one: https://www.alldatasheet.com/html-pdf/179408/ … /HIP6301CB.html .

Mobile CPUs up to Athlon XP Barton are unofficially supported (only problem on my mobile Barton 2500+ is that the max FSB of the board is 133 and the max multiplier of the board is 12.5, so it won't go above 1.6 GHz, but at least it has twice the cache of previos generations. It also works with AMD Geode NX CPUs (highly binned Athlon XP Thoroughbred-B with unlocked multipliers, again up to 12.5), so in theory a wide range of speeds should be accessible.