Fantastic job! Cypress seems to have really sane 2 layer routing compared to Realteks 😮
Couple of notes. Im not poopooing on your hard work, just trying to put out some feedback:
1 you dont want ground noodles connected to real ground by a thin sliver on one side like between:
-PD0 PD1 PD2 PD3 PD4 PD5 PD6
-PD16 20 21 22 23
-three noodles under U5 especially the big one with "designed by MK 2024 (R)" printed over it
-tiny one under U11
-long big one under extended ISA slot
-A2_ISA 3 4 5 6 7
Ground that is not solid plane or densely (<wavelenght) stitched to solid plane no longer works as ground, it works like an antenna and amplifies interference. In the past guard traces were used before we had good modeling and understanding of magnetic propagation on the pcb, they only worked because putting one forced engineers to make more space between signal traces. All those dangling traces between signal tracks just resonate. https://resources.altium.com/p/guard-traces-hit-or-myth
2 whats the deal with 1 ohm R19? Cirrus says something about preventing latchup. Latchup is most likely to happen when input voltage exceeds supply, sudden supply spikes above safety margins is another cause. Putting those resistors will mitigate excessive voltage while making the card more susceptible of inputs 😐 Weird their MCA diagram has those, but ISA one doesnt? Its soo against my intuition, but probably worth it to follow their advice in the end 😐
- extended ISA slot, routing VCC straight to C33 (with another stupid 1ohm resistor) instead of going across the card wouldnt be breaking your ground plane over all those signals.
- omitting ISA oscillator input option will make ground more solid. Currently it leaves a dangling track with very high frequency clock crossing D8-18 and LA lines while breaking ground even when unused. Using ISA 14MHz was a cost cutting measure, nowadays useless.
- pin 159 oscillator goes in a weird around pad way making it go outside of ground plane coverage. Its especially critical to have uninterrupted ground under clock signals.
- separate/isolated analog/digital ground planes is also relic of the past, modern techniques show it doesnt work if it has to cut up ground into multiple islands. https://www.youtube.com/watch?v=XD1jqFaA-uI https://www.youtube.com/watch?v=pgJfOklQwNA Here for example it paradoxically messes with analog signal integrity by making those signals suddenly lose reference. Im fairly certain it only makes things worse for Cirrus recommended design.
- optional EEprom pins also degrade analog video signals by breaking their ground 🙁 best option would be routing those two tracks with jumpers over analog RGB.
- filtering analog VGA looks nice when placed in neat rows, but you got analog B crossing over analog G, and all analog tracks going under (Vias high impedance is really bad for such high speed analog signals) where they arent routed over ground plane. Hurts OCD, but asymmetrical component placement lets you leave Analog signal on top layer over healthy uninterrupted ground.
- H and V syncs cross each other with no ground underneath, swapping filtering sections around solves that.
- 3 amp fuse and thick tracks on Vga Pin 9 is overdoing it 😀 especially considering Cirrus is not even capable of reading Edid.
- looking at https://old.vgamuseum.info/component/content/ … edstar-pro.html it seems Cirrus chip doesnt mind swapping ram address pins around for easier routing. Card in the picture has Pin 153 routed to MA0, but 152 to MA7. This could simplify routing giving some room to stitch more grounds.
- also at lest one tantaum going on teh back would give some precious room between ram and teh chip.
- very long RAS1 under U13 U14 can be avoided, makes it look stupid but ground plane is healthier = shorter cuts = shorter return paths = less interference and crosstalk.
TLDR golden rule is every signal should be as close as possible, preferably over, a ground directly connecting source and destination of said signal with lowest impedance. Signals arent electrons, they are electromagnetic waves and need to close the loop. Closer the ground smaller the field, lower the ground impedance (bigger ground plane = better, traveling over multiple vias = bad) higher the frequency of mitigated interferences.
My attempt at implementing some of above on your 2 layer project with heavy overdoing it via stitched patches:
The attachment render_.png is no longer available
The attachment render_b.png is no longer available
4 layer board of that size would be what, $10 more? for infinitely healthier signal integrity and tons less work. If someone is interested in seeing pcb files I can upload somewhere.
