Maybe found a datasheet. Assuming it works the way I think it does (one jumper pulls up S0 and S1 on the clock chip, the other jumper selects the clock between the clock gen and a crystal socket (that this board doesn't have)):
Jumper 1, 1-2 pulls up S0, Jumper 1 2-3 pulls up S1.
Jumper 1, 1-2-3 might be 40MHz (pulling up s0 and s1). I need to do some testing to make sure it's actually working as I think it is.
These jumpers don't go to the clock chip, at least not to S0, S1, S2. They must be for something else (PCI/ISA dividers?)
There is another 3pin jumper near the CPU labeled clock that seems to go to the clock chip. 1-2 is supposed to be 33MHz, 2-3 is supposed to be 25MHz. The datasheet I found seems to indicate that S0-S2 are active high (no prime bar above the pins on the diagram). This is surprising because S2 is pulled high with a resistor right next to the generator IC. So I'm working on the assumption that they're in fact, active low.
According to the datasheet, 0 0 1 should give me 24MHz and 0 1 0 should give me 32MHz. The three pin header seems to go:
- Either 5V or ground (5V to ground on this board is only 5Ohms, it's hard to tell which is which (!?))
- this goes to S1
- this goes to S0
So, 1-2, the 33MHz setting seems to just be a place to park the jumper, doesn't seem to do anything. Confirmed by leaving the jumper off, still get 33MHz. 2-3 seems to tie S1 and S0 together, meaning the datasheet I have isn't correct. Which isn't that surprising given the active low/high issue above.
TL;DR:
It's almost certainly possible to get 20MHz, 24MHz, 32MHz, 40MHz, 50MHz, 66MHz, 80MHz, and 100MHz from this clock generator by lifting s0-s2 and breaking them out to jumpers. There probably aren't adequate dividers for PCI and ISA bus speeds, but there are probably undocumented settings available given the two 3 pin jumpers that seem to control this. More work than I'm willing to put in, the pins are very very small 😀