Hi byte_76,
Great to hear the patched BIOS works as planned! 😀
However, getting the L1 cache in WB mode is another matter.
The Am5x86 article on my website, that you found earlier, also contains information on how to find the jumper that is connected to the CPU’s WB/WT# pin B-13.
A first step is connecting this pin to Vcc to get the L1 cache in WB, but this will most certainly crash the PC. As you see from the article, a lot of other conditions need to be fulfilled as well, one of which concerns the BIOS.
The 1994 BIOS has only WB enable logic for the Cx486DX(2) and Intel 486DX2WB (P24D), so it doesn’t program the chipset for L1 WB support on any other CPU model, when you set WB in the BIOS Setup.
So another BIOS patch is required, but this will need a full BIOS analysis. Success on this is slim however, as Ali 1429(G) chipset documentation is not available. Also the P24D jumper settings on this board are needed to know how to connect the HITM#, INV, and CACHE# signals between the chipset and CPU.
Not a project with a reasonable chance of success. But when I can find the time, I like to analyze this 1429G chipset L1 WB logic to at least contribute to @Rav’s Universal chipset patcher. project.
Let me know if you ever find the B870 board’s manual with P24D jumper settings. That would help enormously!
Jan