Benedikt wrote on 2025-06-25, 17:25:

PSA: The PCB layout on page two of ISA-CGA6845-1.5.pdf is a largely complete vector drawing of all layers, i.e. you can open it […]
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PSA: The PCB layout on page two of ISA-CGA6845-1.5.pdf is a largely complete vector drawing of all layers, i.e. you can open it in Inkscape and take it apart.

Furthermore, it occurred to me that, since the card has 32 KiB of SRAM, it should be possible to modify it for Plantronics ColorPlus style 16-color graphics.
The hardware part of the modification would only require one bodge wire to the SRAM's highest address line.
We would then also need new bitstreams for the CPLDs, but that should be doable, too.
The memory bandwidth for 320x200x16 and 640x200x4 should be the same as in 80-column text mode.
It should also be possible to fix the wait state generation to get rid of the CGA snow that would otherwise also affect the new modes.

Card and spare CPLDs are on their way. Let's see where this takes us...

Uh, that's fascinating. So you would write the CPLD code from scratch?

root42 wrote on 2025-06-26, 05:23:

Uh, that's fascinating. So you would write the CPLD code from scratch?

The idea is to use a slightly byzantine tool chain consisting of GHDL, a Yosys fork for the ATF15xx CPLDs, and the old Atmel fitters.
That way, everything can be modeled in VHDL instead of CUPL and the resulting library of assorted 74xx logic chip VHDL models can be reused for all sorts of things.

In the meantime my card has arrived and I have started to do some experiments.
I thought that adding a composite output would be an easy first project, but apparently the relevant CPLD pins 61 and 62 do not output what the schematic says they do.

According to the schematic, pin 62 should be CSync and pin 61 should be the modulated NTSC color carrier as a binary signal.
It turns out that one of them carries no signal at all and the other outputs some weird 894 kHz square wave.
The ostensibly unconnected pin 60 is apparently another VSync.

In other words: We are not going to get a simple composite video mod until my VHDL re-implementation of the CPLD logic is done.

My goal for the composite video mod is a split design that merely adds two resistors to the card itself, namely to connect CPLD pins 61 and 62 to the previously unused pin 7 of the DE9 socket, which then outputs a strong CSync signal with modulated color carrier mixed in.
Five additional resistors in a DE9-to-RCA adapter plug would then add the luma signal to the mix and attenuate the whole signal to 1V peak-to-peak.
For the resistor values, I do not intend to copy IBM, because I believe that I can do better.

The following spreadsheet calculation shows why I intend to use the resistor values detailed therein:

The blue curve shows the ideal CVBS luma level of every CGA color, with the exception that color 6 would have been dark yellow instead of brown.
The yellow curve shows the respective CVBS luma levels approximated with the resistor values I determined.
All resistor values are from the E12 series. The odd additional 33Ω for R, G, B and I are already on the card itself, namely between the CPLD and the DE9 socket.
Needless to say, the impedance matching will be far from perfect, but there is only so much that can be done with a passive adapter.

It’s honestly perplexing that a modern CGA device doesn’t have a jumper to set its frequency
15khz
18khz
22khz
32khz

There should be no technical limitation on modern parts running at higher refresh/bandwidths

Hooking up 4bit TTL to any standard monitor digital or analog is trivial

^There were CGA/HGC combo cards that optionally supported 400 line mode for 640x400 Olivetti/AT&T mode.
They had a jumper that caused CGA to be line-doubled all time, but required a monitor capable of ca. 25 KHz sync or something.