just rename .AWD or anythig else to .BIN

Babasha wrote on 2025-12-15, 13:47:

just rename .AWD or anythig else to .BIN

Hi Tomek TRV,

I agree with @Babasha. The .AWD BIOS files are the same binary BIOS files like the .BIN files. The name doesn’t matter.
I've looked into the 0306 latest final release (06/25/1996) BIOS, and it has Am5x86-133 support indeed.

Cheers, Jan

Thank You very much. I will test it.

It looks like these newer BIOS files which can recognize 5x86 are for newer versions of this motherboard. My ancient version A4 don't have BIOS which could recognize this CPU and also support onboard IDE controller. I think (I didn't try it yet) that I can turn off onboard controller and use newer BIOS but I am wondering what other problems can I find. There is some information on TheRetroweb that newer versions are not for this chipset. What should I do??? Probably I will go back to my 486-VIP-IO2 because this fight with Asus cost me too much.

Tomek TRV wrote on 2025-12-15, 19:34:

It looks like these newer BIOS files which can recognize 5x86 are for newer versions of this motherboard. My ancient version A4 don't have BIOS which could recognize this CPU and also support onboard IDE controller. I think (I didn't try it yet) that I can turn off onboard controller and use newer BIOS but I am wondering what other problems can I find. There is some information on TheRetroweb that newer versions are not for this chipset. What should I do??? Probably I will go back to my 486-VIP-IO2 because this fight with Asus cost me too much.

Oh no, you are right. Your present #401A0- 0101 BIOS is the only version that supports the older chipset A4 revision. I didn’t notice that before.

Let me look into the -0101 and -020x BIOS versions to see what can be done.
In the mean time, can you test the Am5x86 when set to x3 multiplier mode and check if it runs and is reported as a DX4 CPU, both with 33 and 40MHz FSB?
If so, I may be able to patch the -0101 BIOS for x4 multiplier support.

I will report back when I have more.

Jan

Today it is too late to test it because I just disassembled everything and mounted 486-VIP-IO2 but I will try tomorrow. I checked a lot settings and I am almost sure that it is working as DX4 120MHz but for sure there was a problem with cache configuration - it is only working in WT mode and still it have a problem with IDE: when I connect anything to second channel it stops to recognize any HDD on primary channel. I know that You are a specialist in the field of BIOS modifications Jan and I really admire what You do.

So I tested it and there is no problem to work as 100 and 120MHz but only in WT mode - cache L1.
It is recognizing my CF card and don't want to recognize HDD. I tested few known good HDD and on the beginning one of them was working but when I connected CD ROM as master on secondary channel motherboard stoped to recognize anything. Now I have my CF card as a master on primary channel and CD ROM as a master on secondary channel and it seems to work ok but why real HDD don't want to work? Strange.

Thanks for the additional tests. This confirms that the Am5x86 is recognized as a DX4-S when in x3 multiplier and L1 cache WT mode, and this is also what I see in the CPU detection table inside the BIOS.

It appeared that the #401A0-0101 (11/23/94) BIOS is a perfect fit for the patches I described in the DIY BIOS Modding guide #part 3:
Re: Diy modding support for k6+And 120gb hard drives into bios roms
and #part 4:
Re: Diy modding support for k6+And 120gb hard drives into bios roms
so you can follow these descriptions to have an idea what I changed in your PVI-486SP3 BIOS.

List of changes/bugfixes:
- Fixed the Year 2094 bug. This bug caused the year to jump forward to 2094 at each boot-up whenever the date was set to 1-1-2000 or later.
- Fixed the 2GB HDD display limit bug for correct drive size indication up to 8GB
- Added detection of the Am5x86 and the Enhanced Am486DX4. Both these CPUs will now be displayed as DX4-S, instead of Unknown or an 80486DX2. They should run fine now, provided they are set to L1 cache WT mode.
- Changed the Busspeed detection to include x4 mode for the Am5x86. (A small remaining cosmetic issue is that 4x33MHz is indicated as 132MHz i.s.o. 133MHz.)

Here is this #401A0-0101 patch J.1 BIOS for you to try:

Note that this patched BIOS doesn’t have any support for L1 cache WB mode (yet).
There isn’t even a BIOS option in the 0101 BIOS to Enable/Disable Internal cache WB, and I’ve never seen a 1994 Award BIOS where this option was automatic. So I’m wondering if the SiS 496/497 Rev A4 chipset even has working L1 WB support.

To find out if the 0101 BIOS has any L1 WB support, like for the i486DX2WB (P24D), I need to disassemble and analyze the BIOS code and this takes some time. I expect to have time for that in about a month.

Please let me know how this 0101 patch J.1 BIOS works with an Am5x86 CPU.
Happy holidays, Jan

Hello
Sorry for answering after such a long time. I am working at sea and I am rarely at home. Thank You Jan for Your time and this pathched BIOS. I just tested it and:
1. cache L2 is not working. I used second set of chips which I know that are ok but nothing changed. Cachechk shows that there is only one level of cache - 16kb. Speedsys also shows one drop of speed at 16kb. Motherboard responds to changes in the jumpers settings because when I set it wrong it don't wanted to work. (but see below)
2. When I set 33MHz x4 on startup screen I have DX4-S 100MHz but Speedsys shows ok 5x86 133,
3. When I set 50MHz x4 on startup screen I have DX4-S 150MHz but Speedsys chows Am486DX4 153 so it is ok, like You wrote.
Once again thank You for what You did. Maybe You have some idea why this L2 cache is not working.
I will be at home for next few days so I can do some more tests.

Correction:
I left everything what I wrote before for Your information.
I didin't even try setting cache into WB mode because You wrote that it is not supported and these problems were in WT mode but when I was writing this post i decided to try WB mode just to see what will happen and I am very happy because in WB mode everything is working fine. Now I have two levels of cache and Speedsys see my CPU as Am486DX4WB 150MHz (3x50) or Am5x86WB 160MHz (4x40).
Great job, thank You very much.

Thanks for reporting back on your tests with the -0101 patch J.1 BIOS.

1. I have no explanation why the L2 cache doesn’t work with the L1 cache in WT, but does work with L1 cache WB. Very weird.
Can you confirm with my CHKCPU CPU Identification Utility that the L1 cache indeed changes from Write-Through to Write-Back when you change JP23 from 2-3 to 3-4?

2. An 100MHz display by the patched BIOS in 33 x 4 mode is unexpected. This should be 132MHz. What does the BIOS show in 40 x 4 and 50 x 3 mode?

I wrote that L1 cache WB is not (yet) supported because I didn’t do anything to the BIOS to add that support for the Am5x86. So your report that it works is another surprise. 😉
Did you try to boot from a DOS floppy in L1 cache WB mode? This is the best test I know to check for correct L1 cache coherency in WB mode.

I will let you know when I start working on the disassembly of this BIOS.
Cheers, Jan

So I tested it.
Ad.1.
Really in WT mode I have only CPU cache (L1). Bios shows that there is 256kb L2 cache but Speedsys and Cachechk see only L1 cache. CHKCPU shows correct settings when I am changing JP23 between WT and WB mode.

Ad.2.
See below but all tests were done with settings like here: https://theretroweb.com/motherboard/manual/ad … 18656392446.pdf for Am5x86-P75. I was only changing JP22 (multiplier) nad JP23 (cache mode) and of course FSB. Maybe something would change if I would change all jumpers for correct CPU?

33x4 Bios shows DX4-S CPU at 100MHz
CHKCPU:
AMD 5x86-133 P75(x5)
Internal CPU speed 134MHz
Clock mul. 4.0
Bus clock 33,5MHz
Speedsys: AMD AM5x86WB 133MHz

40x4 Bios shows DX4-S CPU at 132 MHz
CHKCPU:
AMD 5x86-133 P75(x5)
Internal CPU speed 159,5 MHz
Clock mul. 4.0
Bus clock speed 39,8MHz
Speedsys: AMD AM5x86WB 160MHz

50x3 Bios shows DX4-S CPU at 150MHz
CHKCPU
AMD 486DX4 Enhanced or AMD 5x86 in 3x clock mode
Internal CPU speed 150,1 MHz
Clock mul. 3.0
Bus clock 50MHz
Speedsys: AMD Am486DX4WB at 150 MHz

Tomek TRV wrote on 2026-01-13, 12:25:

So I tested it. Ad.1. Really in WT mode I have only CPU cache (L1). Bios shows that there is 256kb L2 cache but Speedsys and Ca […]
Show full quote

So I tested it.
Ad.1.
Really in WT mode I have only CPU cache (L1). Bios shows that there is 256kb L2 cache but Speedsys and Cachechk see only L1 cache. CHKCPU shows correct settings when I am changing JP23 between WT and WB mode.

Ad.2.
See below but all tests were done with settings like here: https://theretroweb.com/motherboard/manual/ad … 18656392446.pdf for Am5x86-P75. I was only changing JP22 (multiplier) nad JP23 (cache mode) and of course FSB. Maybe something would change if I would change all jumpers for correct CPU?

33x4 Bios shows DX4-S CPU at 100MHz
CHKCPU:
AMD 5x86-133 P75(x5)
Internal CPU speed 134MHz
Clock mul. 4.0
Bus clock 33,5MHz
Speedsys: AMD AM5x86WB 133MHz

40x4 Bios shows DX4-S CPU at 132 MHz
CHKCPU:
AMD 5x86-133 P75(x5)
Internal CPU speed 159,5 MHz
Clock mul. 4.0
Bus clock speed 39,8MHz
Speedsys: AMD AM5x86WB 160MHz

50x3 Bios shows DX4-S CPU at 150MHz
CHKCPU
AMD 486DX4 Enhanced or AMD 5x86 in 3x clock mode
Internal CPU speed 150,1 MHz
Clock mul. 3.0
Bus clock 50MHz
Speedsys: AMD Am486DX4WB at 150 MHz

Thanks for the additional tests.

Ad.1. I’ve still no idea what could cause this. I will look into the BIOS code to see what is going on here.

Ad.2. I see a pattern here: Only when the x4 mode is set, the reported CPU speed is the value for a one step lower FSB. So 4x33 is reported as 4x25 (100MHz) and 4x40 is shown as 4x33 (132MHz). This is clearly a BIOS issue where the FSB is incorrectly detected when the CPU is in x4 multiplier mode, while in x3 mode all is correct.
I’ve seen this issue once before in a patched Award BIOS for the PCChips M912. I never found the cause then, but now I have another case and hopefully this helps in finding this bug.

Talk to you later,
Jan

You also wrote that it would be good if I try to start my computer from floppy disc in L1 cache WB mode. I don't know what You mean but for tests I am always starting this computer with pressed shift so it is pure DOS.

Tomek TRV wrote on 2026-01-14, 18:35:

You also wrote that it would be good if I try to start my computer from floppy disc in L1 cache WB mode. I don't know what You mean but for tests I am always starting this computer with pressed shift so it is pure DOS.

Actually, I did mean to start from a DOS 5 or 6 boot floppy.

The floppy disk controller uses DMA to transfer its data to memory, which forces the CPU to relinquish control of the bus to the DMA controller. The CPU and DMA controller are both Bus-Master controllers and only one can be active on the bus at any given time.
When the CPU senses that the DMA controller addresses a “stale” memory location for which it has updated data in its L1 cache which has not yet been write back to memory, it forces the DMA controller off the bus and writes the appropriate L1 cache line back to memory. After that, control is passed back to the DMA controller.

This CPU-DMA “dance” uses several signal lines between the CPU and the chipset to ensure that cache coherency is always maintained. These signal lines are only used by L1 cache WB capable CPUs, and in addition the BIOS has to program the chipset to enable these WB protocol signals.

So when booting from a DOS floppy doesn’t crash, the L1 cache WB protocol works as planned. Note that booting from an IDE drive always keeps the CPU in control and any missing jumper on one of the WB signals, or lack of chipset programming by the BIOS, is not easily detected.

Greetings, Jan

Now I understand but probably I destroyed floppy controller 🙁
When I started to play with this motherboard I installed MS DOS from floppies but when I tried to use 5x86 and there were problems I was connecting and disconnecting everything many times. Now I saw that when I turn on floppy controller in BIOS computer can't start co I started checking cables and - disaster. I had data cable conected in wrong way on 3,5 inch floppy A and on 5,25 inch floppy B it was connected ok. After connecting only 3,5 inch floppy the light on it is still on and computer is hanging. I have to use some other controller. I have many of them. It's a pity that the 5.25 disk drive also looks broken. I will do some more tests tomorrow.

So I tested everything and by the way built another 486 machine, the same like my firs computer: 486DX/2 80 MHz, 8MB RAM, Trident 9440VLB. Luckily it looks like only 3,5 inch floppy drive is broken. Floppy controller and 5,25 drive are ok.

Hi Tomek TRV,

Here is an update on the patched PVI-486SP3 #401A0-0101 (11/23/94) BIOS for your board with the revision A4 chipset.

I’ve completed the BIOS disassembly and have been analyzing the L1 cache WB logic. Although this -0101 BIOS has no “Internal Cache WT/WB” option in the BIOS Setup, I found that it does automatically enable L1 WB support for the P24D (i486DX2WB), P24T (iPOD63/83), and Cyrix 486DX(2) CPUs.
So there is no L1 WB support for the iDX4WB, Enhanced Am486DX2/DX4, Am5x86, Cyrix 486DX4, or Cx5x86.

I’m now working on a patch to add automatic L1 WB support for at least the iDX4WB, Enhanced Am486DX2/DX4, and Am5x86.
I’m also looking into the FSB detect issue in x4 mode, but I haven’t found a clue yet.

Greetings, Jan.

Thank You Jan for what You are doing. I have some free days now so I will play with this cmputer. How can I repay You for this work?
You wrote:
"Here is an update on the patched PVI-486SP3 #401A0-0101 (11/23/94) BIOS for your board with the revision A4 chipset."
but I don't see anything to download.
Best regards
Tomasz

Tomek TRV wrote on 2026-02-13, 19:31:

Thank You Jan for what You are doing. I have some free days now so I will play with this cmputer. How can I repay You for this w […]
Show full quote

Thank You Jan for what You are doing. I have some free days now so I will play with this cmputer. How can I repay You for this work?
You wrote:
"Here is an update on the patched PVI-486SP3 #401A0-0101 (11/23/94) BIOS for your board with the revision A4 chipset."
but I don't see anything to download.
Best regards
Tomasz

Hi Tomasz,

That “update” was only to tell you what progress I made, analyzing your BIOS.
So no new patched BIOS yet, sorry. 😉

In the mean time I’ve successfully added detection of the iDX4WB, Enhanced Am486DX2/DX4, and Am5x86.

This new code can also detect if these CPUs are running in L1 cache WT or WB mode. But I still have to add the logic to automatically enable the chipset’s WB protocol signals when the CPU is in L1 WB mode.

So still some work to do, but hopefully I do have a download for you in my next reply.
Cheers, Jan

Hi Tomasz,

The new #401A0-0101 patch J.2 BIOS for your Asus PVI-486SP3 with the Revision A4 chipset is ready now, and here is a copy.

For those who haven’t read the whole thread, the November 1994 #401A0-0101 BIOS is the latest version for PVI-486SP3 boards with the SiS496/497 Revision A4 chipset. Later 020x and 030x BIOS versions can’t be used on this board, so a patched -0101 BIOS was needed for Am5x86 support.

This is the change list for this 0101_J2 BIOS:
- Added detection of the Enhanced Am486DX2/DX4, and of the Am5x86 CPU when set for x4 multiplier mode
- Added proper display of the Enhanced Am486DX2 and Enhanced Am486DX4 CPUs
- Added proper display of the Am5x86 CPU when set to x4 multiplier mode. In x3 multiplier mode the Am5x86 will be displayed as an Enhanced Am486DX4 CPU.
- Added automatic L1 cache Write-Back support for the Am5x86, Enh Am486DX4, Enh Am486DX2, and iDX4WB. This new logic detects if these CPUs are running in L1 cache WT or WB mode, and automatically enables the chipset’s WB protocol signals when the CPU is in L1 WB mode.
- Changed the Busspeed detection to include x4 mode for the Am5x86 to correct the CPU speed display and Auto configuration timings
- Fixed the Year 2094 bug
- Fixed the 2GB HDD display limit bug for correct drive size indication up to 8GB.

For testing the new automatic L1 cache Write-Back logic, I have written a SIS496.CFG configuration file for the CTCHIPZ DOS program, and here is a copy.
In the zip I’ve also packed the latest CTCHIPZ.EXE v3.7 and the Ctchipz.doc documentation.

Chipset register 40h controls the L1 cache WT/WB protocol settings.
From the DOS prompt, you can directly see the reg 40h setting with the following CTCHIPZ command:

CTCHIPZ SIS496 40

When you do this with the previous patch J.1 BIOS and your Am5x86, you will probably see this screen, where the Reg 40h contents is 06h:

With the patch J.2 BIOS, the Reg 40h contents should change to 6Ah, indicating correct support of the L1 cache WB protocol:

With the Enter key, you can step through all chipset registers.
Reg 42h is also interesting and shows the L2 cache programming.
The ESC key returns you to the DOS prompt.

One final remark about this patched BIOS, I haven’t yet found the cause of the deviating CPU speed reporting by the BIOS, when using the Am5x86 x4 mode.
So you may still see the 4x33 mode shown as 100MHz and 4x40 as 133MHz by this patch J.2 BIOS. I’m still working on this, so expect a final J.3 BIOS in the future. 😉

Happy testing,
Jan