it’s my own project which incorporates both bridge and sound chips on a single pcb. this special header on the mobo inspired me trying it. yes master# signal is pulled up to 5v line via 4.7k resistor.

6300esb datasheet has e2h register related to legacy sound cards io, but it’s stated as not validated whatever it means. i decided to give a try but stuck at the very beginning.

anthony wrote on 2026-02-14, 22:18:

it’s my own project which incorporates both bridge and sound chips on a single pcb. this special header on the mobo inspired me trying it. yes master# signal is pulled up to 5v line via 4.7k resistor.

6300esb datasheet has e2h register related to legacy sound cards io, but it’s stated as not validated whatever it means. i decided to give a try but stuck at the very beginning.

Hmmm... looks like older ICHs have only two generic decode ranges (E4h and ECh) for LPC, compared to later ones which has four. This kind of matches the functionality of the Winbond LPC-ISA bridge, W83626.

The register E2H you mentioned is no longer present on ICH5 datasheet. Bits related to sound cards in E6H are also marked as "Reserved" there. I don't think they're that relevant, however, as at least with MIDI and SB decode ranges they are too few for some modern sound cards, including GUS.

I think you'll have to look for earlier boards (late PIII or early P4) with ISA slots that incorporated LPC-ISA instead of PCI-ISA, to see whether these decode range registers had any use back then.

Alright, what is the differecne between 0.3 and 0.4 revisions of this bridge board?

anthony wrote on 2026-02-16, 02:24:

Alright, what is the differecne between 0.3 and 0.4 revisions of this bridge board?

IIRC just some silkscreen cleanups.

It's just that LSS10999 had trouble getting 0.3 to work, but IIRC also had some dodgy bridge chips so it might just have been that

One more mobo tested: MSI Z87M Gaming, LDRQ1 exposed/available/working.
Quite serious VRM, Z87 Gryphon class.
Mobo has no VGA/DVI ports, all of the graphics ports - digital (DP/HDMI).
No issues with ISA PnP ports ranges availability.
Terrible USB mices support in DOS: LMB has both issues: not clicking and excessive over clicking (1 physical click registered as several clicks).
Lot of cheap/expensive mices tested, seems polling rate related, because very basic mices has less issues (just not registering sometimes LMB clicks: you click = nothing happens)
KB/Mouse while plugged both in USB ports jam each other in DOS badly as well: the same issues like with mouse, but now with keyboard keys: not registering or overregistering key down.
One should use PS/2 mouse only - hours without issues (combined port, only one device allowed). Actually boardview clearly shows all the lines connected (both KB/MS data/clock to the PS/2 header), Y-cables of mine are 1:1 to both legs, after rewiring I'll report back. The same wiring in Gigabyte's Z87M/B85M D3H and I suppose Asrock's Z87M/B85M as well.
External graphics card + PS/2 mouse - success.
Overall ? Recommended. LDRQ1 pin location attached.

I just tested a v0.4 board I assembled a few weeks ago. Looks like it's really working. I wonder what might be the real reason behind the troubles I had with v0.3 assemblies.

Haven't tested it in-depth. I powered it on with an ISA POST card over my B450M testbed and I could see outputs on the card, as well as being able to show arbitrary values I wrote to port 80h. This is all I could achieve on AMD hardware at the moment.

A few pages back, someone with an ASUS board was saying they couldn't get LPC working.

I've done about half the "PCR" file for the LPC device in WPCREDIT on a H55 chipset and it seems to work.

I think these sections may be important. I suspect ISA IRQ routing might be switched off.
It's an ancient tool, (WPCREDIT) but the config file is straightforward enough, and it works in 9x.

1(60:7)=Interrupt Routing Enable PIRQA	0=route to ISA compatible 1=route to 8259PIC
2(60:6)=reserved
3(60:5)=reserved
4(60:4)=reserved
5(60:3)=IRQ	0000,0001,0010,1000,1101 reserved
6(60:2)=IRQ	0011=irq3,0100=irq4,0101=irq5,0110=irq6,0111=irq7
7(60:1)=IRQ	1001=irq9,1010=irq10,1011=irq11,1100=irq12
8(60:0)=IRQ	1110=irq14,1111=irq15
9
10(61:7)=Interrupt Routing Enable PIRQB	0=route to ISA compatible 1=route to 8259PIC
11(61:6)=reserved
12(61:5)=reserved
13(61:4)=reserved
14(61:3)=IRQ	0000,0001,0010,1000,1101 reserved
15(61:2)=IRQ	0011=irq3,0100=irq4,0101=irq5,0110=irq6,0111=irq7
16(61:1)=IRQ	1001=irq9,1010=irq10,1011=irq11,1100=irq12
17(61:0)=IRQ	1110=irq14,1111=irq15
18
19(62:7)=Interrupt Routing Enable PIRQC	0=route to ISA compatible 1=route to 8259PIC
20(62:6)=reserved
21(62:5)=reserved
22(62:4)=reserved
23(62:3)=IRQ	0000,0001,0010,1000,1101 reserved
24(62:2)=IRQ	0011=irq3,0100=irq4,0101=irq5,0110=irq6,0111=irq7
25(62:1)=IRQ	1001=irq9,1010=irq10,1011=irq11,1100=irq12
26(62:0)=IRQ	1110=irq14,1111=irq15
27
28(63:7)=Interrupt Routing Enable PIRQD	0=route to ISA compatible 1=route to 8259PIC
29(63:6)=reserved
30(63:5)=reserved
31(63:4)=reserved
32(63:3)=IRQ	0000,0001,0010,1000,1101 reserved
33(63:2)=IRQ	0011=irq3,0100=irq4,0101=irq5,0110=irq6,0111=irq7
34(63:1)=IRQ	1001=irq9,1010=irq10,1011=irq11,1100=irq12
35(63:0)=IRQ	1110=irq14,1111=irq15
36
37
38
3969:7)=Interrupt Routing Enable PIRQF	0=route to ISA compatible 1=route to 8259PIC
40(69:6)=reserved
41(69:5)=reserved
42(69:4)=reserved
43(69:3)=IRQ	0000,0001,0010,1000,1101 reserved
44(69:2)=IRQ	0011=irq3,0100=irq4,0101=irq5,0110=irq6,0111=irq7
45(69:1)=IRQ	1001=irq9,1010=irq10,1011=irq11,1100=irq12
46(69:0)=IRQ	1110=irq14,1111=irq15
47
48(6A:7)=Interrupt Routing Enable PIRQG	0=route to ISA compatible 1=route to 8259PIC
49(6A:6)=reserved
50(6A:5)=reserved
51(6A:4)=reserved
52(6A:3)=IRQ	0000,0001,0010,1000,1101 reserved
53(6A:2)=IRQ	0011=irq3,0100=irq4,0101=irq5,0110=irq6,0111=irq7
54(6A:1)=IRQ	1001=irq9,1010=irq10,1011=irq11,1100=irq12
55(6A:0)=IRQ	1110=irq14,1111=irq15
56
57(6B:7)=Interrupt Routing Enable PIRQH	0=route to ISA compatible 1=route to 8259PIC
58(6B:6)=reserved
59(6B:5)=reserved
60(6B:4)=reserved

61(6B:3)=IRQ	0000,0001,0010,1000,1101 reserved
62(6B:2)=IRQ	0011=irq3,0100=irq4,0101=irq5,0110=irq6,0111=irq7
63(6B:1)=IRQ	1001=irq9,1010=irq10,1011=irq11,1100=irq12
64(6B:0)=IRQ	1110=irq14,1111=irq15

They probably correlate with the later chipsets but if you can be bothered looking through your datasheet, and matching it up, I'm curious to know.

If you haven't figured it out, it decides whether the ISA IRQs get mapped to PCI IRQs A>H and which one is mapped to what.
Call it a route table if you like.

EG Offset 6B reading 0xxx0101 = map from IRQ5 to IRQH (I think) Maybe someone will correct me.

There are remnants of the original file I was editing - some via chipset.

myne wrote on Today, 01:05:

A few pages back, someone with an ASUS board was saying they couldn't get LPC working. […]
Show full quote

A few pages back, someone with an ASUS board was saying they couldn't get LPC working.

I've done about half the "PCR" file for the LPC device in WPCREDIT on a H55 chipset and it seems to work.

I think these sections may be important. I suspect ISA IRQ routing might be switched off.
It's an ancient tool, (WPCREDIT) but the config file is straightforward enough, and it works in 9x.

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1(60:7)=Interrupt Routing Enable PIRQA	0=route to ISA compatible 1=route to 8259PIC
2(60:6)=reserved
3(60:5)=reserved
4(60:4)=reserved
5(60:3)=IRQ	0000,0001,0010,1000,1101 reserved
6(60:2)=IRQ	0011=irq3,0100=irq4,0101=irq5,0110=irq6,0111=irq7
7(60:1)=IRQ	1001=irq9,1010=irq10,1011=irq11,1100=irq12
8(60:0)=IRQ	1110=irq14,1111=irq15
9
10(61:7)=Interrupt Routing Enable PIRQB	0=route to ISA compatible 1=route to 8259PIC
11(61:6)=reserved
12(61:5)=reserved
13(61:4)=reserved
14(61:3)=IRQ	0000,0001,0010,1000,1101 reserved
15(61:2)=IRQ	0011=irq3,0100=irq4,0101=irq5,0110=irq6,0111=irq7
16(61:1)=IRQ	1001=irq9,1010=irq10,1011=irq11,1100=irq12
17(61:0)=IRQ	1110=irq14,1111=irq15
18
19(62:7)=Interrupt Routing Enable PIRQC	0=route to ISA compatible 1=route to 8259PIC
20(62:6)=reserved
21(62:5)=reserved
22(62:4)=reserved
23(62:3)=IRQ	0000,0001,0010,1000,1101 reserved
24(62:2)=IRQ	0011=irq3,0100=irq4,0101=irq5,0110=irq6,0111=irq7
25(62:1)=IRQ	1001=irq9,1010=irq10,1011=irq11,1100=irq12
26(62:0)=IRQ	1110=irq14,1111=irq15
27
28(63:7)=Interrupt Routing Enable PIRQD	0=route to ISA compatible 1=route to 8259PIC
29(63:6)=reserved
30(63:5)=reserved
31(63:4)=reserved
32(63:3)=IRQ	0000,0001,0010,1000,1101 reserved
33(63:2)=IRQ	0011=irq3,0100=irq4,0101=irq5,0110=irq6,0111=irq7
34(63:1)=IRQ	1001=irq9,1010=irq10,1011=irq11,1100=irq12
35(63:0)=IRQ	1110=irq14,1111=irq15
36
37
38
3969:7)=Interrupt Routing Enable PIRQF	0=route to ISA compatible 1=route to 8259PIC
40(69:6)=reserved
41(69:5)=reserved
42(69:4)=reserved
43(69:3)=IRQ	0000,0001,0010,1000,1101 reserved
44(69:2)=IRQ	0011=irq3,0100=irq4,0101=irq5,0110=irq6,0111=irq7
45(69:1)=IRQ	1001=irq9,1010=irq10,1011=irq11,1100=irq12
46(69:0)=IRQ	1110=irq14,1111=irq15
47
48(6A:7)=Interrupt Routing Enable PIRQG	0=route to ISA compatible 1=route to 8259PIC
49(6A:6)=reserved
50(6A:5)=reserved
51(6A:4)=reserved
52(6A:3)=IRQ	0000,0001,0010,1000,1101 reserved
53(6A:2)=IRQ	0011=irq3,0100=irq4,0101=irq5,0110=irq6,0111=irq7
54(6A:1)=IRQ	1001=irq9,1010=irq10,1011=irq11,1100=irq12
55(6A:0)=IRQ	1110=irq14,1111=irq15
56
57(6B:7)=Interrupt Routing Enable PIRQH	0=route to ISA compatible 1=route to 8259PIC
58(6B:6)=reserved
59(6B:5)=reserved
60(6B:4)=reserved

…Show last 4 lines

61(6B:3)=IRQ	0000,0001,0010,1000,1101 reserved
62(6B:2)=IRQ	0011=irq3,0100=irq4,0101=irq5,0110=irq6,0111=irq7
63(6B:1)=IRQ	1001=irq9,1010=irq10,1011=irq11,1100=irq12
64(6B:0)=IRQ	1110=irq14,1111=irq15

They probably correlate with the later chipsets but if you can be bothered looking through your datasheet, and matching it up, I'm curious to know.

If you haven't figured it out, it decides whether the ISA IRQs get mapped to PCI IRQs A>H and which one is mapped to what.
Call it a route table if you like.

EG Offset 6B reading 0xxx0101 = map from IRQ5 to IRQH (I think) Maybe someone will correct me.

There are remnants of the original file I was editing - some via chipset.

I'm aware of these IRQ routing registers (60h and 68h). AFAIK these seems to be read only once you're already in an OS (including DOS). Don't know if it's possible to reimplement "PnP/PCI configuration" menu in modern UEFI so these registers can be fiddled somewhat.

For me, these registers can serve as a hint to note which PIRQ line is active and which IRQ has been taken. So take note of which register is reading 05h or 07h and see if you can disable enough onboard devices to turn off certain PIRQ lines (the byte will then read 80h) or make it use a different IRQ.

PS: IIRC if you're in an APIC-enabled operating system PIRQ lines will go to APIC (you'll see the PCI hardware taking IRQs 16 and above from Device Manager), so these registers become less relevant in that scope.

I managed to change them and totally crash the win98 H55 AMIBIOS8 I was testing it on.
YMMV.

Try wpcredit if you're bored. When I get time, I should finish it. It just takes a while.