Just added a link to my post on the EGA/(S)VGA SLR behaviour, as well as some discoveries about it's latching and wrapping behaviour during the different graphics modes.
Ofc I don't think that the SLR bit would have any effect in text modes? Since there's nothing extra to rotate in text mode, I guess it would cause the same effect as 256-color mode shifting (the same pixels repeating over and over due to the same inputs being used)?
Edit: Just improved the Tseng chips to properly use the EGA emulation bit to perform the horizontal and vertical blank end properly (masking to 5 bits instead of 6 and 8 bits respectively).
Edit: Just improved the shift registers to operate in big-endian mode properly on little-endian machines, since plane 0=byte 0 of the value read from VRAM.
Input Status 0 register: bits 5-6 are binary numbers from the feature connector. Their inputs for either FC0 set (lower bits) and FC1 set (higher bits)
Input status 1 register: bit 1 indicates light pen trigger set. bit 2 indicates light pen switch is open (not pressed?). Bits 4-5 report video status MUX (see color plane enable register) on EGA, required to POST.
1video_probe_CGA_or_EGA proc near 2 push ax 3 push cx 4 push dx 5 mov dx, IO_Port_3DAh_CRTC_Status 6 xor al, al 7 out dx, al ; Video: bits 0-1 control 8 ; Feature Control outputs FC0 and FC1 9 in al, dx ; Video status bits: 10 ; 0: retrace. 1=display is in vert or horiz retrace. 11 ; 1: 1=light pen is triggered; 0=armed 12 ; 2: 1=light pen switch is open; 0=closed 13 ; 3: 1=vertical sync pulse is occurring. 14 mov cl, 3 15 shr al, cl 16 and al, 00000110b 17 mov ch, al 18 xor al, 00000010b 19 out dx, al ; Video: bits 0-1 control 20 ; Feature Control outputs FC0 and FC1 21 push dx 22 pop dx 23 in al, dx ; Video status bits: 24 ; 0: retrace. 1=display is in vert or horiz retrace. 25 ; 1: 1=light pen is triggered; 0=armed 26 ; 2: 1=light pen switch is open; 0=closed 27 ; 3: 1=vertical sync pulse is occurring. 28 shr al, cl 29 and al, 00000110b 30 xor al, 00000010b 31 out dx, al ; Video: bits 0-1 control 32 ; Feature Control outputs FC0 and FC1 33 xor al, ch 34 cmp al, ch 35 mov al, 0 36 jnz short end 37 or ch, 21h 38 mov al, cs:39h 39 40end: 41 out dx, al ; Video: bits 0-1 control 42 ; Feature Control outputs FC0 and FC1 43 mov cs:39h, al 44 mov cs:46h, ch 45 pop dx 46 pop cx 47 pop ax 48 retn 49video_probe_CGA_or_EGA endp
EDIT: or are status 1 register Bits 4-5 reflecting FC0 FC1 only on CGA? then this function would make perfect sense, would only write to cs:39h cs:46h on CGA card.
That's how the EGA BIOS seems to use it during it's POST, to determine it's flags to store in the BDA (switches and feature bits routine). Just read with FC0 set for the low 2 bits, then again with FC1 set for the high 2 bits.