Reply 240 of 254, by Falcosoft
- Rank
- l33t
Marco Pistella wrote on 2026-05-23, 08:01:First of all, a big thank you to everyone who has been testing NEWAX 0.11 and providing feedback. Your reports are extremely val […]
First of all, a big thank you to everyone who has been testing NEWAX 0.11 and providing feedback. Your reports are extremely valuable and are directly driving the development of the next version.
A specific request: if you have pre-G80 hardware, please test latest NEWAX version (linked above - not GitHub version) and report your results. The current Detect_Supported_Nvidia routine has a known false positive on NV44 discrete (GeForce 6200 confirmed), and improving the detection for pre-G80 hardware requires real-world data from as many cards as possible. PCI_ID, revision and SUBSYS_ID from the /S output are particularly useful.@Falcosoft
Hi Falcosoft, thank you for sharing the TSR — the approach is interesting and the vsync loop logic is correct in principle. However I found this issues:
1. BL=82h → BL=02h conversion is incorrect and potentially serious
BL=82h (schedule display start, VESA 3.0 asynchronous) has completely different semantics and parameters from BL=02h (set display start during retrace, synchronous). Silently converting one to the other produces incorrect behavior on any VBIOS that implements BL=02h correctly, and the caller has no way to know the conversion happened.
2. Hang on monochrome systems
The vsync loop reads unconditionally from port 3DAh. On monochrome systems the status register is at 3BAh — the loop will wait forever for a transition that will never come on that port.
3. Hang on Intel HD graphics and similar
On many Intel integrated GPUs (SandyBridge, IvyBridge, Haswell and later) port 3DAh does not behave as a standard VGA status register. The vsync loop will hang indefinitely — ironically on exactly the hardware you mentioned as having vsync problems.
4. BL not preserved on return
The caller passes BL=80h. The TSR modifies it to BL=00h before PUSHA, calls the VBIOS, then IRET. The caller receives BL=00h on return instead of the original BL=80h. A TSR must preserve input registers that are not defined as output by the VESA specification.
5. Spurious POP AX at tsrinit entry
JMP does not push anything on the stack. The POP AX at the start of tsrinit consumes the DOS initial return address (0000h) that was pushed by DOS at program load — this is harmless in practice but fragile and unnecessary.
Hi,
1. OK, I thought the 02h/82h variants are only differ in the expected data type (that is 00h/80h expects pixel data while 02h/82h expects byte data).
2. I cannot confirm this hanging problem. It works correctly on my Intel Pentium B940, I7-3632QM and I7-4770K both with X-VESA and FALSSAN3. So some other conditions have to be present on your system(s) that cause infinite loops.
It is not true that 'generally' port 3DAh does not behave as a standard VGA status register (at least it behaves as such on all of my tested Intel GFX systems). More feedback from others with Intel integrated GFX are welcome to investigate this issue further.
@Edit:
Here is my test video from my i7-3632QM Ivy Bridge system (as can be seen at 1st run there is no v-sync in either X-VESA or FALSSAN3 but after running VSYNCFIX v-sync works in both):
https://youtu.be/yolIVmB-ZwE
(BTW, Have you just read about this infinite loop problem somewhere or you actually tested and experienced it?)
3.I do not think monochrome systems are practically relevant in the context of this TSR 😀
4. Yes, but according to VBE specification the content of BL is not defined at output (only BH that is not modified). Also in case of many VBE functions it is explicitly stated that "All other registers are preserved" but Function 07 is NOT one of them. So I do not think and I also do not experience that software would rely on it.
5. Yep, it could be fixed.