OK, so today my giant carton of every type of resistor showed up, so it was time for soldering.

To recap - the board uses an LT1085CT regulator near the CPU socket. I measured the original voltage at the LT1085 tab:

1Original Vcore:
2~3.437V idle
3~3.438V under TESTCAB / SpeedSys load

So the regulator was stable and had essentially no droop, but it was only providing about 3.44V.

The LT1085CT pinout is:

1Pin 1 = ADJ
2Pin 2 = VOUT
3Pin 3 = VIN
4Tab = VOUT

I measured the existing feedback path:

1Pin 1 / ADJ to Pin 2 / VOUT: ~0.618k ohms
2Pin 1 / ADJ to ground: ~1.049k ohms

The lower feedback resistor is the blue SMD resistor marked 1051, which measured about 1.049k ohms and goes from ADJ to ground.

The mod was to add a resistor in parallel with the VOUT-to-ADJ resistor path, by soldering a through-hole resistor on the underside of the board between LT1085 pin 1 and pin 2:

1Added resistor:
28.2k ohm, 1% metal film
3
4Connection:
5LT1085 pin 1 / ADJ <-> LT1085 pin 2 / VOUT
6
7Do not connect to pin 3 / VIN.

Before soldering, the resistance between pin 1 and pin 2 was:

1~0.618k ohms

The 8.2k resistor itself measured:

18.29k ohms

After soldering it across pin 1 and pin 2, the measured resistance between those pins dropped to:

1~0.574k ohms

I started it up, and here's what the voltage regulator measured:

1~3.599V

Which is just about perfect if I am to understand that this chip is rated for 3.6V maximum. I reassembled the board and confirmed the voltage was still around 3.59V after power-up.

Before changing jumpers back to 160MHz, I kept the system at the known-stable 3x40 / 120MHz setting and tested the mod:

140MHz bus
23x multiplier = 120MHz
3Vcore ~3.59V
4External cache enabled

That passed my TESTCAB copy-file test and SpeedSys normally, so the voltage mod itself did not appear to introduce instability.

I then changed only the multiplier jumper back from 3x to 4x:

1JP24:
21-2 = 3x
33-4 = 4x

The system is now back at:

140MHz bus
24x multiplier
3AMD-X5-133ADZ at ~160MHz
4Vcore ~3.59V

Early testing looks promising so far. Both benchmarks have passed and there have been no crashes. I'm going to keep testing and we'll see where we wind up.

I had an Adrian Black style "IT FREAKING WORKED" moment already. Given that I have minimal electronics and soldering skills and had no confidence in what I was doing here, I'm surprised in a good way. This forum plus a bit of ChatGPT input might have unlocked the key to 160MHz for this board. A huge thanks to jakethompson1 and the other ideas on this thread so far. Woot!

Hi rjbrown99,

That is a nice mod you did, increasing the CPU voltage to 3.6V to get a stable 160MHz overclock on your Am5x86-133! I was less lucky with my Am5x86. Even at 4V I couldn’t get it to run stable 150 or 160MHz. 🙁
Anyway, I followed your endeavors with this GA-486VF board with interest. You already got great help from the community and i like to add some.

From your earlier Speedsys test pictures I noticed that you run the Am5x86 in L1 cache Write-Through mode. Note that the Internal Cache WB/WT option in the BIOS only works on Cyrix CPUs. Intel and AMD socket 3 parts don’t have software control for L1 Cache WB and need to have pin B13 pulled up to enable L1 Write-Back mode.
This is usually done by a jumper that connects this pin B13 to Vcc. Some additional CPU-chipset connections have to be made as well to get the WB mode work correctly.
In addition, the BIOS must program the chipset to enable the L1 Write-Back protocol signals.
Details about all this can be found in my old Am5x86 article:
http://www.steunebrink.info/amd5x86.htm

The 1994 Award BIOS doesn’t support the L1 WB logic for the DX4 and 5x86 CPUs, so you definitely need a BIOS update if you want the extra ~8% performance provided by L1 WB. But that’s the reason I’m writing. 😀

Did you see this thread from 4 years ago?
160mhz CPU on VLB Motherboard ?
I adapted an 11/28/95 SiS471 BIOS for the GA-486VS and you can download this GA-486VS Rev. J.1 BIOS from my second reply in this thread.
This BIOS supports all socket 3 CPUs, including the Cyrix 5x86 and Am5x86 in L1 cache WB and x4 multiplier mode. It’s also free of the year 2094 and 2GB HDD display limit bugs and supports IDE drives up to 8GiB.
Further down in this thread, TheMobRules uploaded a Rev. J.2 version of this BIOS with the Register 72h tweak that increases memory performance considerably.
I recommend this Rev. J.2 BIOS for a GA-486VF/VS upgrade.

Yes, the GA-486VF and GA-486VS are practically identical and use the same BIOS. The only difference between these boards is the type of RAM slots used (30-pin or 72-pin).

When running this 11/28/1995 BIOS, you still need the jumper settings for L1 Cache WB mode.
This is what @TheMobRules wrote in the above thread:

TheMobRules wrote on 2022-05-10, 08:24:

For future reference, here are the settings for both of these CPUs. Just follow the manual for an Intel DX4 and set these additi […]
Show full quote

For future reference, here are the settings for both of these CPUs. Just follow the manual for an Intel DX4 and set these additional jumpers:
• JP21: close 1-2 (this sets the hardware trap for WB L1 of the chipset)
• JP24: close 2-5 (to connect HITM# line from the CPU to the chipset) and 3-4 on the 5x86 only (it sets the DX4 multiplier to x2, which is x4 for the 5x86)
• JP30: closed (to pull the WB/WT# line high, enabling WB mode)
Note 1: there is no jumper for the INV pin, it seems to be permanently connected to Vcc, no jumper for CACHE# either
Note 2: if you set L1 to WB mode, DRAM Write Burst option in the BIOS needs to be disabled, otherwise it will hang when trying to boot MS-DOS

Hope this helps.
Cheers, Jan

Very interesting, thanks very much for that - I had not come across that limitation around the AMD CPU itself. Earlier in this thread it was suggested that the BIOS mod was needed and I have that done and the chip is just sitting to the side while I test and dial in each setting in the original BIOS. Didn't realize a pin change was also required. I'll read up on that in detail. And I didn't see your BIOS thread, but if it works for this board I'll pull that down and give it a try as well. That is super helpful and should improve my benchmarks.

Before I give it a try, my next step is to take this original bios and figure out the optimal settings with it - one at a time, with reboot and retry of my testing process and benchmarks. I want to land on a stable but performant baseline for 160 then graduate to the next round of changes. The BIOS you directed me to is 100% next on the list after the baseline.

I'm using an Adaptec AHA-2842A so the IDE bits aren't quite as relevant right now. I am planning to try the Adaptec BIOS mod for that as well to add large drive support.

I am also debating if I should buy 32MB of 50ns RAM from Atheatos and try it with 256KB of cache (assuming bank interleaving would be enabled). But that's for yet another day, I also have a fair amount of sanding and painting left to do for the case this is going into. Very hard to find cases in good shape so I'm doing a complete refurb of an intact but rusty purchase from eBay.

Oh, and I also have an IBM 5x86-100 on the way from Amibay - tested on a very similar Gigabyte board @ 120MHz. So I'll have two viable options to try for the CPU.

@chkcpu one clarification and follow-on question for you.

Intel and AMD socket 3 parts don’t have software control for L1 Cache WB and need to have pin B13 pulled up to enable L1 Write-Back mode.

Clarification: My motherboard has JP11: AMD CPU Selection Jumper. I have this open to indicate to the Board that it is an AMD CPU. As I understand your web page, this is the CPU/hardware side of enabling write-back. Nothing needs to happen to the actual physical pin B13 on the CPU itself.

Question: The above means that it's just the BIOS mod to enable write-back. And I did have that on a chip already, but I'm going to explore the one on your thread which fixes other issues. Any idea if you expect it will work on my board, as I have 30 pin SIMMS with 8 slots total whereas the GA-486-VS (which was the originating board of the BIOS on that thread) has 4 RAM slots? This was the issue I hit with the Mr Bios for this chipset, it was for a board with 4 RAM slots and wouldn't boot on mine.

I'll likely try it either way, but maybe another modbin change would be required on my board.

There is no broad reason to have a jumper for AMD CPU yes/no. What is probably happening is that AMD offered the DX4 in two pinouts. The original aka NV8T uses a custom pinout. The newer one aka SV8B aka Enhanced Am486 uses the P24D aka 486DX2-66WB pinout. The Am5x86 also uses the P24D pinout. It should be jumpered the same as an Intel 486DX2-66WB (except 3.6V instead of 5V) or the same as an Intel DX4WB (except 2x/4x instead of 3x).

rjbrown99 wrote on 2026-07-08, 00:18:

Very interesting, thanks very much for that - I had not come across that limitation around the AMD CPU itself. Earlier in this thread it was suggested that the BIOS mod was needed and I have that done and the chip is just sitting to the side while I test and dial in each setting in the original BIOS. Didn't realize a pin change was also required. I'll read up on that in detail.

Reading the above reply, I sense a confusion between L1 and L2 cache issues. Let me clarify.

The external L2 cache on the motherboard is fully controlled by the chipset. The L2 cache can operate in either WT or WB mode, as controlled by the External Cache WB/WT option in the BIOS Setup. The register 72h bit 2 tweak from earlier in this thread improves performance by enabling a dirty-bit in the Tag-RAM when the L2 cache operates in WB mode.

The internal L1 cache inside the CPU is controlled by the CPU itself and is completely independent of the L2 cache. So if the CPU supports it, the L1 cache can be operated in WT or WB mode, independent of the L2 cache WT/WB mode.
Most 486 CPUs only support the L1 cache WT mode but several Cyrix models, the Intel 486DX2WB (P24D), Intel DX4WB (has &EW markings), Intel POD83 (P24T), AMD Enhanced 486DX2, AMD Enhanced 486DX4, and the Am5x86-133 support both L1 cache WT and WB modes.
Except for the POD83, all above WB capable Intel and AMD models are switched from WT to WB via CPU pin-B13. This is where jumper JP30 on the GA-486VF/S is for. The motherboard manual indicates this jumper for the P24D only, but it functions the same on the other L1 WB capable CPU from both Intel and AMD.
(Note that the POD83 uses pin T1 for WT/WB selection.)

The only time when the chipset is involved in the L1 cache data handling, is when the L1 cache is in WB mode and the CPU has relinquished control to another busmaster controller like the DMA controller. A good example is the floppy disk controller that uses DMA to transfer its data to memory.
While during a DMA transfer the CPU is not active on the bus, it does “snoop” the bus. When the CPU senses that the DMA controller addresses a “stale” memory location for which it has updated data in its L1 cache which has not yet been written back to memory, it signals the chipset via its HITM pin (Hit Modified). This causes the chipset to force the DMA controller off the bus and grants the bus to the CPU to write the appropriate L1 cache line back to memory. After that, control is passed back to the DMA controller.
This CPU-DMA “dance” uses several signal lines between the CPU and the chipset, of which HITM is the most important, to ensure that cache coherency is always maintained. These signal lines are only used by L1 cache WB capable CPUs, and in addition the BIOS has to program the chipset to enable these WB protocol signals.

Both Intel and AMD WB capable CPUs use the same protocol and signals. So just as jakethompson1 indicated, don’t be fooled by an AMD CPU jumper and use the P24D jumper settings for the Am5x86, except of course for the CPU voltage and multiplier jumpers.

For the SiS471 chipset there are two additional chipset pin trappings that tell the chipset what kind of CPU it is dealing with.

As shown in the above picture from the SiS471 datasheet, the CPU Type Select trappings use the DACK1# and DACK0# chipset pins. Although it is only indicated for the P24D and P24T, these pins must both be pulled high for any Intel and AMD L1 WB capable CPU, to enable the L1 WB protocol signals.
These trappings are usually controlled by 2 jumpers. On the GA-486VF/S I know one is JP21 that needs 1-2 closed. The other is probably JP11 that needs 1-2 closed as well.

I still believe that the 11/28/95 patch J.2 BIOS and the correct jumper settings will give you proper L1 cache WB support on your GA-486VF Rev 6.
I hope the above helps with that.

Cheers, Jan