I set up jumpers based on some pictures online and installed TI486DX2-66. It's alive!

There are still some issues.
I plugged in the 512k cache, but the POST interface shows no L2 cache. AIDA also reported that no L2 cache was detected.

do you see any L2 cache on the pcb?

rasz_pl wrote on 2026-04-10, 20:47:

do you see any L2 cache on the pcb?

256K L2 CACHE

"The selected attachment does not exist anymore."

Im sorry, I missed "I plugged in the 512k cache" after just looking at picture of naked board
Jumpers will depend on the type/capacity of sram you plugged in. Afaik its impossible to make universal wiring that will take any capacity - you need jumpers to rewire certain pins. Here is example of a L2 cache module I reverse engineered some time ago https://github.com/raszpl/FIC-486-GAC-2-Cache … al%20rev2.4.png
there are 6 resistors (playing the role of jumpers) that one needs to connect or disconnect depending on populated SRAM to make the cache cover its address range.

To find which jumpers are cache related use multimeter continuity/beeping function and find jumpers connected to SRAM chip address lines.

Did you ever find out more details about the jumpers and/or the cache?

Playing around, trial and error and a bit of doodling together with AI Chat
Trying to figure out the board I received. It has an AMD 133 MHz and it was set to 75 MHz. Jumpers 18, 19 and 20 is adjusting FSB:

FSB Control (JP18, JP19, JP20)

Located just above the 16bit ISA part right under the VT82C416 chip.

1JP18  JP19  JP20  | FSB MHz
2------------------+--------
3ON    ON    ON    | 16 MHz
4OFF   ON    ON    | 25 MHz
5OFF   OFF   OFF   | 33 MHz
6OFF   OFF   ON   | 40 MHz

Multiplier Control (JP9)

Located on the jumper collection just above the voltage regulator. Both JP5 and JP9 seem to be connected to the R17 CLKMUL point on the socket.

1JP9   | Multiplier
2------+-----------
3UP    | 4x
4NONE  | 3x
5DOWN  | 3x (???)