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First post, by CkRtech

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Hey all - I need a reality check.

I recently upgraded my Epox P55-TF, Intel 430fx system to 64 MB of RAM (2x 32MB in Bank 0). The board has 256k of pipeline burst cache and a W24129AK-12 Tag chip in the DIP socket.

Doing almost anything in Windows 98 SE leads to page faults.

These issues can be bypassed by limiting RAM to 32MB via system.ini or keeping 64 MB and disabling L2 entirely. System runs stable either way.

I do not have the ability to toggle between WB and WT in my BIOS, but I assume switching to WT and running 64 MB would also work.

As I understand it, 256k of cache can do 64MB of RAM in WT or 32MB in WB. If you want 64MB in WB, you need 512k of cache.

I recently acquired a 256k Coast module to double system cache to 512k. It includes a UT6164JC-15 Tag chip . I do not believe that tag can cover 512k of cache. I left the DIP Tag in the socket and kinda just... ran with them both.

I have the same issues in Windows 98 SE as I did before the cache upgrade.

I assume that I Windows 98 SE will be happy if I can just disable the tag on the Coast module and use the DIP Tag to handle all 512k of cache in WB mode.

Anyone want to weigh in? Am I barking up the right tree?

Reply 1 of 3, by rmay635703

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I would clean all the cache and memory contacts and examine for any coorsion or damage.

What speed/brand/type of ram are you using? (The size of the cache-256/512 shouldn’t do anything to the addressable range of the cache)
Also installing two separate cache systems doesn’t work.

You could test a low bus speed like 50mhz and see if everything stays the same.

• L2 Cache Size Requirements: To cache the maximum 64MB of RAM, the system requires a standard 256KB of Level 2 (L2) cache. Upgrading the motherboard to 512KB of L2 cache will improve your overall cache hit rates slightly, but it will not increase the 64MB cacheable memory boundary.
Hardware TAG RAM Requirements
The amount of memory the chipset can cache is dictated by its TAG RAM configuration:
• A standard 8-bit TAG RAM chip (often a 15ns or faster SRAM chip near the cache slots) is integrated or paired natively to map exactly 64MB of RAM using Write-Back mode.

Reply 2 of 3, by jakethompson1

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The 430FX datasheet says that the status/modified bits are internal and only the tag address bits are stored externally, so that is why write-back doesn't halve the cacheable area like it would on a 486 chipset using 7+1 mode.

Reply 3 of 3, by CkRtech

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Thank you both for your replies.

It would appear that both the manual and the silkscreen for the RAM banks on the Epox P55-TF are incorrect. Bank 0 and Bank 1 are reversed.

I moved both RAM sticks to "Bank 1," and have not encountered any page faults in Windows 98 SE.