CuPid wrote on 2020-04-15, 10:55:

Sorry for the delay guys. […]
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Sorry for the delay guys.

>feipoa : I've edited the original post with the required CPUs to be tested.

>CoffeeOne : Thanks for your tests. Could you please post a TXT report ?

>phantom_pl : thanks !

Here is a txt from the Micronics ASIC EISA computer.
The crash is now solved, I don't need to disable something in the ini.
Maybe you can improve: Mainboard Info and BIOS version, that looks ugly 😁

feipoa wrote on 2020-04-18, 01:00:

CuPiD> Is there another revision of CPU-Z you wanted me to test on the SXL-50 for the case of L1 being disabled? If not, I'll move onto another CPU on your wish list.

The CR0 reading needs some preparation (accessing to CR0 requires a new function in the VxD), so please feel free to move onto another processor.

CuPiD> I decided to run CPU-Z on my cased SXL2-66 system with a ULSI DX2-66 FPU in Windows 95c. CPU-Z starts up, but after a few seconds, the screen goes black and stays black. Reboot Win95 and scandisk runs. Is there anything you want me to do to debug this? HWiNFO also had a fair bit of issues with my SXL2-66 system, but he seems to have found workarounds and temp fixes for the time being.

feipoa wrote on 2020-04-20, 08:27:

CuPiD> I decided to run CPU-Z on my cased SXL2-66 system with a ULSI DX2-66 FPU in Windows 95c. CPU-Z starts up, but after a few seconds, the screen goes black and stays black. Reboot Win95 and scandisk runs. Is there anything you want me to do to debug this? HWiNFO also had a fair bit of issues with my SXL2-66 system, but he seems to have found workarounds and temp fixes for the time being.

If no cpuz.ini was created, can you please download that one into the same directory as the exe and run the program ?
If cpuz.ini exists, you can just change that entry :

1Sensor=0

(if it works, please send me a report, so I'll make the fix permanent).

Thanks feipoa !

The ini filed corrected the hang. Attached is the report file.

I also ran the benchmark. TI 486SXL2-66 with ULSI US83D87-C-66 on an AMI Mark V Baby Screamer motherboard based on the VLSI Topcat chipset.

Looks like kixs system was a bit faster for CPU, whereas mine was much faster with FPU due to the clock doubled FPU. Do you have any plans to add FPU detection to CPU-Z?

Something else I noticed is the idle load of CPU-Z. It consumes between 21-29% of the CPU at idle. Is this normal?

feipoa wrote on 2020-04-20, 09:43:

Looks like kixs system was a bit faster for CPU, whereas mine was much faster with FPU due to the clock doubled FPU. Do you have any plans to add FPU detection to CPU-Z?

I started working on that but didn't go very far. One of the tricks used for detection required an exception handling, that is unchieveable under win9x, so I stopped (maybe too early).

feipoa wrote on 2020-04-20, 09:43:

Something else I noticed is the idle load of CPU-Z. It consumes between 21-29% of the CPU at idle. Is this normal?

Not normal, but this is not a suprise. The diet to adapt the code should be more intensive for CPUs below 200MHz.

Wintop is part of powertoys for windows 95, is it ? it is available for free ?

Yeah, I beleive it was part of the Win95 PowerTools that you could download online from MS once upon a time. This university has it available: http://misweb.cbi.msstate.edu/~rpearson/tips/wintop.html

The SXL2 will run on NT4. Do you want me to run CPU-Z in NT4 once you add the FPU detection trick?

feipoa wrote on 2020-04-20, 10:28:

The SXL2 will run on NT4. Do you want me to run CPU-Z in NT4 once you add the FPU detection trick?

Thanks, but most lkely I'll revisit the process to avoid that specific test because the support of win9x is my 1st priority (at least for that version).

Attached is the report for a Cyrix DRx2-66 with a Cyrix FasMath CX-83D87 running at 33 MHz. Benchmarks are CPU at 22.9 and FPU at 60.8.

CPU-Z failed to report the L1 cache on both tabs. The DRx2 has 1 KB of L1 cache. I think its 2-way set associative.

Thanks feipoa. I hope you can keep it installed for some time, I'd like to try to fix several points on it.

How much time do you think you need? My guess is that it will be there a week.

feipoa wrote on 2020-04-30, 18:51:

How much time do you think you need? My guess is that it will be there a week.

It will be more than enough, a couple of days should be OK. Thank you !

There are some information about the DRx2 that I can't find, any clue would be welcome.
- what is the manufacturing process ? My 1st guess is 1 um (1000 nm) but it is mentionned nowhere.
- was there any SRx/DRx/DRu (w/o the 2x clock) released ?
- what is the difference between the DRu/DRu2 and DRx/DRx2 ?

Unlike the SXL2, I believe all DRx2 and DRu2's have 2x mode enabled by default. I don't think it can be put in 1x mode, but I could be wrong. I've never seen a DRx or SRx without the '2'.

I vaguely recall the DRu2 being discussed in the forum before but don't recall the difference with the DRx2 - I think they are the same. I'll ask around.

My guess would be the process for the DRx2 is the same as the DLC and SXL, but I don't know. I'll ask around.

This is the information I received from somebody else concerning the DRu2. Apparently the DRu2 isn't so much a CPU alone but is rather a CPU kit, which contains an external circuit that doubles the incoming frequency (I assume a PLL of some sort) and handles hardware L1 cache invalidation. Seems that a standard DLC CPU was used in these kits, but the CPU or perhaps the whole kit was renamed the DRu2. Cyrix added the clock doubling and cache invalidation circuitry into the CPU die for the DRx2. If the DRu2 used a standard DLC chip, I'm guessing it only did 20/40 clock doubling, but I suppose Cyrix could have also cherry picked some for 25/50, but I doubt it.

I don't think I've seen anyone online with any test results for a DRu2 and I doubt anyone testing CPU-Z will have access to one.

The process used for the DRx2 and DRu2 are likely the same as that for the DLC.

Thanks feipoa.

Concerning the L1 : there is a very complete databook of the 486DLC here : http://www.bitsavers.org/components/cyrix/Cyr … Sheet_May92.pdf
It mentions (page 1.2) that the L1 cache can be configured as direct-mapped or as 2-way. The setting is configured with bit 6 of CCR0 (the same bit that does the 2x on Ti SXL2).
I can't remember having seen such a BIOS option on a mainboard tho.

Yes, that is correct. I've viewed the DLC and SXL databook many times. I also have never seen a BIOS which has an option to set the DLC's cache to direct-mapped or 2-way. I've always left the DLC in 2-way mode as I assumed it is faster for most applications. The SXL2 is always in 2-way mode. I've also never seen a BIOS which can enable 2x on the SXL, but I'm sure boards which have specific support for the SXL2 must have a 2x option in the BIOS.

I am curious if the DRx2 has an option for 2-way set associative or direct-mapped, or if it is always in 2-way mode. I don't think I've tried to change its L1 mode. Should I try this to see if CPU-Z gets it right?

feipoa wrote on 2020-05-02, 08:22:

I am curious if the DRx2 has an option for 2-way set associative or direct-mapped, or if it is always in 2-way mode. I don't think I've tried to change its L1 mode. Should I try this to see if CPU-Z gets it right?

The current version won't even see the L1, I'll post a new one in a few.
I don't know if the L1 associativity setting can be changed on the fly, but it would be interesting to see if there is a big difference in performance.

It can be changed on the fly in DOS; I've changed it before. Whether the cache style got changed or not, I don't recall. I'll have to run the DOOM benchmark.

Here is a new version.
http://download.cpuid.com/betas/cpuz_w95.zip

CuPid wrote on 2020-05-02, 09:03:

Here is a new version.
http://download.cpuid.com/betas/cpuz_w95.zip

Does this fix K5 crash?