The lowest grey one essentially disables writeback funciton, making a cache flush every time a write happens as it connects Invalidate pin of an Intel/AMD CPU to read/write strobe. For Cyrix the middle pin is SUSPA which the right connection is toward right, where it is pulled up and suspend is disabled that way.
This jumper can make performance very slow, like on some motherboards in writeback mode except there's no dirty bit so they are flushing all the time and bringing performace down.
The second line from below is two jumpers, 123 and 45. 123 handle SMI and HITM pins, for Cyrix in needs to be 12 for mobo SMI to connect to CPU SMI, for Intel/AMD it needs to be 23 for the two to connect.
45 and the neigbhors right below are for L1 WB/WT control. Lower for WT, higher for WT.
I am confident the settings I traced out are correct, unless there are revisions of the board that do change meaning of the jumpers.
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