kalohimal wrote on 2020-06-18, 06:03:

simworld wrote on 2020-06-18, 05:53:

Good works... keep it up. I from Johor Malaysia too. […]
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Good works... keep it up. I from Johor Malaysia too.

Your project spice me with idea building my a ultimate retro PC..

Hopefully these hardware works
Duo Core E2160
512mb DDR (lower it frrom 2G to 512mb for Win98)
GF8500??

Umm....hopefully it works.

Glad to hear from a fellow Malaysian. Which motherboard are you planning to use? If you're planning to triple boot DOS/Win98/XP, boards with i815 and earlier chipset will be the best. Oh and I think GF8500 has no Win98 drivers too.

Yeah, when I saw this post, kinda excited that someone just around me. 🤣
omg....8500 dont have driver for win98.. in that case, maybe find other choice.

I plan use GA-EP31-DS3L , test install win98 before last time and if no mistake there's one driver couldn't located.
other option I have
Via C3 Eden embeded ITX,
Intel 810 cs S370 with cpu option celeron 366, celeron 600, p3 800, tualatin

if you need any test on any setup, can let me know if I can help, but need to tell me what you want to test.

actually all while i am looking at a setup that can fit DOS (FAT partition), Win98 (FAT partition), XP (NTFS partition), W7 (NTFS partition)
all dump into 1 rig without switching the hardware with 1 graphic card wiht 1G RAM
Do you think possible?

Purpose is to act as a diagnosis system. So whatever Sata, IDE CD, file transfer etc all can works in 1 roof

simworld wrote on 2020-06-19, 06:12:

Yeah, when I saw this post, kinda excited that someone just around me. LOL omg....8500 dont have driver for win98.. in that case […]
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kalohimal wrote on 2020-06-18, 06:03:

simworld wrote on 2020-06-18, 05:53:

Good works... keep it up. I from Johor Malaysia too. […]
Show full quote

Good works... keep it up. I from Johor Malaysia too.

Your project spice me with idea building my a ultimate retro PC..

Hopefully these hardware works
Duo Core E2160
512mb DDR (lower it frrom 2G to 512mb for Win98)
GF8500??

Umm....hopefully it works.

Glad to hear from a fellow Malaysian. Which motherboard are you planning to use? If you're planning to triple boot DOS/Win98/XP, boards with i815 and earlier chipset will be the best. Oh and I think GF8500 has no Win98 drivers too.

Yeah, when I saw this post, kinda excited that someone just around me. 🤣
omg....8500 dont have driver for win98.. in that case, maybe find other choice.

I plan use GA-EP31-DS3L , test install win98 before last time and if no mistake there's one driver couldn't located.
other option I have
Via C3 Eden embeded ITX,
Intel 810 cs S370 with cpu option celeron 366, celeron 600, p3 800, tualatin

if you need any test on any setup, can let me know if I can help, but need to tell me what you want to test.

actually all while i am looking at a setup that can fit DOS (FAT partition), Win98 (FAT partition), XP (NTFS partition), W7 (NTFS partition)
all dump into 1 rig without switching the hardware with 1 graphic card wiht 1G RAM
Do you think possible?

Purpose is to act as a diagnosis system. So whatever Sata, IDE CD, file transfer etc all can works in 1 roof

If you want to have DOS + Win98 + XP then the best bet is the i810 board. GA-EP31-DS3L is a P31/G31 board and has no Win98 driver. Also i810 won't support Tualatin CPUs. Or you could try the Via C3 Eden (not sure which chipset yours is using). For GPU if you want to go with GeForce then the last one with Win98 driver support is GF6xxx series. Oh and if you want to use 1GB ram with Win98 you'll need to patch the ini file.

And yes it will really be great if you are willing to help out with the C3 testing.

Btw did you get your ITX C3 Eden locally in JB? If so which store has it? I might consider getting one if its not too expensive.

Thanks for all the advice.

My Via C3 is Nehemiah core running at 1Ghz

Never tried CPUspd with it before, but setmul gives me the following result

3Dbench score
@ 1Ghz (default) = 390.8
@ 1Ghz (L2 cache disable) = 408.1 <-- weird score
@ 1Ghz (L1 cache disable) = 11.8
@ 533Mhz with Setmul (default) = 281.6 <-- I think this is equivalent to Pentium II 300Mhz
@ 533Mhz with Setmul (L2 cache disable) = 307.2 <-- weird score
@ 533Mhz with Setmul (L1 cache disable) = 9.7

I got the board from my friend in Taiwan. But you can try the following place. I do remember can bargin till like rm90 only 😁
And probably you can find plenty of "oldies" there..
https://www.lelong.com.my/epia-pd-mini-itx-ma … 7-01-Sale-I.htm

simworld wrote on 2020-06-19, 15:30:

Thanks for all the advice. […]
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Thanks for all the advice.

My Via C3 is Nehemiah core running at 1Ghz

Never tried CPUspd with it before, but setmul gives me the following result

3Dbench score
@ 1Ghz (default) = 390.8
@ 1Ghz (L2 cache disable) = 408.1 <-- weird score
@ 1Ghz (L1 cache disable) = 11.8
@ 533Mhz with Setmul (default) = 281.6 <-- I think this is equivalent to Pentium II 300Mhz
@ 533Mhz with Setmul (L2 cache disable) = 307.2 <-- weird score
@ 533Mhz with Setmul (L1 cache disable) = 9.7

I got the board from my friend in Taiwan. But you can try the following place. I do remember can bargin till like rm90 only 😁
And probably you can find plenty of "oldies" there..
https://www.lelong.com.my/epia-pd-mini-itx-ma … 7-01-Sale-I.htm

Thanks! Oh this shop. I've been there before and bought a few mobos from them. Will go & check out the ITX boards this week.

Good. Tell me what's the board speed... I am pretty attracted by the C3 500mhz..but it's very hard to find one.

I went to the shop today, the owner said the VIA C3 ITX board was already sold, they just never update the listing 😒

Hi kalohimal,

I'm very happy to see somebody is still developing this theme. My regards and good luck!
I'm not a programmer, I was not building MSRED+CACHECTL but these two utilities were built by my task, my request and my testing. Programmer is i8088.

CR0 register disables all cache system. It is impossible to disable L1 separately without disabling all cache system.
L2 can be disabled when total cache system + L1 is enabled. To disable L2 separately (if I remember correctly) we should disable totalcache+L1, disable L2, enable totalcache+L1. To enable L2 again we should disable totalcache+L1, enable L2, enable totalcache+L1.

The register for L2 is not CR0. It is MSR 0x11e (except NetBurst). Values: BE702009=disabled; BE702109=enabled.

You can ask i8088 about it. He will tell you much more and much better than me. Download please his ASM from CACHECTL 0.92 version. It's free.

PARUS wrote on 2020-06-20, 08:47:

Hi kalohimal, […]
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Hi kalohimal,

I'm very happy to see somebody is still developing this theme. My regards and good luck!
I'm not a programmer, I was not building MSRED+CACHECTL but these two utilities were built by my task, my request and my testing. Programmer is i8088.

CR0 register disables all cache system. It is impossible to disable L1 separately without disabling all cache system.
L2 can be disabled when total cache system + L1 is enabled. To disable L2 separately (if I remember correctly) we should disable totalcache+L1, disable L2, enable totalcache+L1. To enable L2 again we should disable totalcache+L1, enable L2, enable totalcache+L1.

The register for L2 is not CR0. It is MSR 0x11e (except NetBurst). Values: BE702009=disabled; BE702109=enabled.

You can ask i8088 about it. He will tell you much more and much better than me. Download please his ASM from CACHECTL 0.92 version. It's free.

Great info, thank you very much! I disable CR0 and then the RAM caching by turning off the cache enable in the MTRR (memory type range register, MSR 2fffh). MTRR is availble for CPU starting from Pentium Pro, so it works for Netburst as well. No sure if the MTRR is considered L2 though... I'll check out MSR 0x11e, with the MSR number and value available it should be quite easy. Thanks again!

CPUSPD version 1.4 released:

• Added support for VIA C3 CPUs: Samuel, Samuel 2, Ezra, Ezra-T, and Nehemiah.
• Added L2 cache control for Intel family 6 CPUs: Pentium 3 (Katmai, Coppermine, Tualatin), Pentium M, Core, Core 2.
• Added south bridge database support for throttling, in addition to ACPI. This is to support systems without ACPI implementation in BIOS (e.g. POS machines, thin clients, etc). The program will first use ACPI to try finding the throttle port. If ACPI is not available, it will then fallback to the database.
• Added PCI device scan to help identify the south bridge devices.

Note: CPUSPD.SBI file must be in the same folder as CPUSPD.EXE. It is a text file containing south bridges programming information. New south bridges can be added by editing this file.

New commands added:

• c2[d|e] - c2d = disable L2 cache, c2e = enable L2 cache. Note: Intel family 6 L2 cache can only be enabled/disabled separately when L1 cache is enabled. If L1 is disabled, L2 will also be disabled.
• p - scan and display all PCI devices.
• pd[xxxx:yyyy] - dump all PCI devices configuration spaces if run without any parameters, or dump the device specified by xxxx:yyyy, where xxxx is the vendor id and yyyy is the device id.
• pdi - dump the PCI configuration spaces of ISA/LPC/other bridges (which contain the power management module in the south bridge).

Credit to PARUS for providing information on P6 L2 cache control programming.

Please download from first post.

Next revision... perhaps to include AMD K10 multiplier support per Falcosoft's suggestion? I hesitate to include CPUs beyond K8/Core2, as their chipsets no longer support Windows 98, hence they are not ideal for retro gaming, although they could still be used for DOS gaming if slowed down enough.

kalohimal, thank you very much! I don't have enough time today for test, use and have fun for our retro rigs, decisions.

Tell me please do you use MSR 19Ah for CPU throttling? Not chipset+FSB throttling by southbridge but skipping CPU clock cycles. It's ODCM. I tried it in DOS by MSRED program and was in delight. For example we start Core2/PentiumE CPU at FSB400, set multiplier 8. Then set ODCM to 87,5% (or 1/8). The CPU becomes to skip 7 tacts along and make each eighth tact effective. And in fact we get multiplier 1 indeed, 100 MHz.

Old DOS games very like small and integer-valued CPU multiplier toward FSB. 1, 2, 3, 4. Integer-valued and small (I repeat), it is one of guarantors for qualitative throttling for old (~early 90s) and oldest DOS games.

More examples (very useful with P4 processors):
Multiplier x12 + ODCM 75% (1/4) = real multiplier x3
Multiplier x16 + ODCM 87,5% (1/8) = real multiplier x2
Multiplier x20 +ODCM 75% (1/4) = real multiplier x5

We can use combination of FSB and CPU (ODCM) throttling for best and most bug-free results.

kalohimal wrote on 2020-07-08, 14:45:

Next revision... perhaps to include AMD K10 multiplier support per Falcosoft's suggestion? I hesitate to include CPUs beyond K8/Core2, as their chipsets no longer support Windows 98, hence they are not ideal for retro gaming, although they could still be used for DOS gaming if slowed down enough.

An unofficial ICH7 Win98 driver exists and it is VERY working 😀 Besides, there are some awesome motherboards on i865 chipset which support Core 2 family.
I know about nForce3 board (of course ASRock!) which supports K10. And K10 architecture has minimum able mul x0.5, i.e. it will be CPU 100 MHz at FSB 200MHz (HyperTransport 800MHz).

PARUS wrote on 2020-07-09, 02:33:

kalohimal, thank you very much! I don't have enough time today for test, use and have fun for our retro rigs, decisions. […]
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kalohimal, thank you very much! I don't have enough time today for test, use and have fun for our retro rigs, decisions.

Tell me please do you use MSR 19Ah for CPU throttling? Not chipset+FSB throttling by southbridge but skipping CPU clock cycles. It's ODCM. I tried it in DOS by MSRED program and was in delight. For example we start Core2/PentiumE CPU at FSB400, set multiplier 8. Then set ODCM to 87,5% (or 1/8). The CPU becomes to skip 7 tacts along and make each eighth tact effective. And in fact we get multiplier 1 indeed, 100 MHz.

Old DOS games very like small and integer-valued CPU multiplier toward FSB. 1, 2, 3, 4. Integer-valued and small (I repeat), it is one of guarantors for qualitative throttling for old (~early 90s) and oldest DOS games.

More examples (very useful with P4 processors):
Multiplier x12 + ODCM 75% (1/4) = real multiplier x3
Multiplier x16 + ODCM 87,5% (1/8) = real multiplier x2
Multiplier x20 +ODCM 75% (1/4) = real multiplier x5

We can use combination of FSB and CPU (ODCM) throttling for best and most bug-free results.

I didn't, as I originally thought it's the same as south bridge throttling. Now that you mentioned it, this clock modulation is located inside the CPU and is different. Very interesting, I will take a more detailed look later.

PARUS wrote on 2020-07-09, 02:51:

An unofficial ICH7 Win98 driver exists and it is VERY working 😀 Besides, there are some awesome motherboards on i865 chipset which support Core 2 family.
I know about nForce3 board (of course ASRock!) which supports K10. And K10 architecture has minimum able mul x0.5, i.e. it will be CPU 100 MHz at FSB 200MHz (HyperTransport 800MHz).

Nvidia nForce series chipsets are a bitch to support, as there are no public documents available, even for non proprietary things like PCI configuration registers. Till now I still couldn't get my program to work with any of the nForce chips, even via ACPI. There must be some proprietary enable register somewhere, which we will never know without the datasheets. I tried Throttle.exe and it's in the same situation. So nForce throttling via south bridge is currently unable to support. K10 CPU multiplier though is a possibility.

Yes! ODCM is different and it gives us much more scope. We can use ODCM without chipset throttling and in most cases eliminate "error 200". We can use ODCM+cache disabling and in many cases get 386 speeds without chipset throttling. We all know that major chipset throttling may cause key/mouse issues (freezes, failures). And know for a long time that major chipset throttling with big multiplier may cause in-game issues. ODCM solves it. In fact our throttling becomes full, flexible and complete with ODCM.

Will this tool do Branch Prediction Disable and Internal-Cache Disable for Via C3 CPU's like Setmul does? It would be great if it did along with the inbuilt Throttle ability. I currently use just Setmul and Rayers SMB for Multi/Cache and FSB control but if i could use CPUSPD to do Multi/Cache & Throttle Control along with SMB i think it would be a very powerful combo, especially for Nehemiah where there is that hole in the 486 speeds. If you could also implement the FSB ability too like is done in Rayers tool would make this the ultimate program for slowdown!

I can take a look, but as far as possible I'm trying to avoid duplicating the efforts with what Setmul already have, since it is really no point in doing so. Adding to the difficulty is I do not have any VIA C3 CPUs, so developing for them is very hard as I have no means of testing and debugging the program. I'm aware of RayeR's SMB tool which uses the SMbus for FSB control. He had done a tremendous job on it and had spent about 5 years in its development. Again perhaps there is no point in duplicating the efforts of what other tools can already offer. But I might slowly add some of these features to CPUSPD when I have time though (e.g. separate L2 cache control for K5/K6, etc), just for the fun of it. But the current main focus is still Intel Pentium 4 & Core/Core 2. 😀

@PARUS

I'll start working on it. It's quite simple to include so maybe just a few days of programming and testing time will do.

Edit: ok it is not so simple. For CPUs with single core and no multithread then it's straight forward. For CPU with multithread, all logical processors must be set, otherwise it will not work properly. This is again another multi processor headache. In the document there is also a line that says: "For the P6 family processors, on-demand clock modulation was implemented through the chipset, which controlled clock modulation through the processor’s STPCLK# pin." so it seems this is applicable to Pentium 4 only?

I have found that ODCM for all NetBurst and all Core2 families is setting up only by one (same for all) specific register 0x19A and it works perfectly. And I can say exactly: it's not seems, it's for sure applicable to Pentium 4, Pentium D, Pentium 4M, Pentium M, Core 2 Duo, Pentium Dual Core 65 and 45 nm (didn't check only Core 2 Quad).
I wasn't looking ODCM at earlier P6 architectures (P2-P3) because I have socket-478, socket-775 motherboards with ISA bus and they are awesome. Besides I never heard about effective cycles skipping technology on Pentium Pro/2/3 CPUs. If I'm not mistake this feature was started on NetBurst generation. And next, I don't understand "was implemented through the chipset, which controlled clock modulation through the processor’s STPCLK# pin". How? This function is CPU specified via its own MSR. And Pentium 2/3 haven't this function in that kind which is present on P4 and later.

According to the docs, ODCM was originally intended for thermal throttling of the CPU, so that the CPU could throttle down when overheating is detected. I checked the msr tables for PD, Core, and Core2, the ODCM msr does exist in them so I'm not sure why Intel put that statement (It's on page 14-30, section 14.7.3, "Intel 64 and IA-32 Architecture Software Developer's Manual, Volume 3, May 2018").

Anyway I've already written the code for this feature. So far it looks real good tested on P4-3GHz Prescott.
Doom real ticks:

• with ODCM off => 610 ticks
• with ODCM = 1 => 1693 ticks (~Am486DX4-120)
• with ODCM = 1 and south bridge throttle = 1 => 16996 ticks (~386DX-25)
• with ODCM = 1 and cache disabled => 74635 (~80286-8) took close to 1 hour to run!

I dare not test ODCM=1 and throttle=1 and cache disabled, as I could imagine it will be unbearably slow and would take forever to run 🤣.

Next things to test: ODCM behavior in P4 with hyperthreading on, and multi cores (PD, Core2).

It is unfortunate that AMD CPUs do not have this msr. Previously I favor AMD more than Intel, but with ODCM now I think they are on par. This also makes P4 a more interesting platform for retro gaming.

I'll do more testing on various platforms and processors (PD, core2, etc) before releasing it. Thanks again for the great help PARUS!