Jackhead wrote on 2025-05-21, 10:08:

I found another SL49P that would match my first CPU. Will get it in the next days. Till than i tested that dummy cpu that comes […]
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I found another SL49P that would match my first CPU. Will get it in the next days. Till than i tested that dummy cpu that comes with my board.
Installed win2k on a SSD over a flashed SIL3114 sata controller. System runs really fast with single core alone.
Not sure its because the 2GB RAM or the 1MB L2, but definitely faster as a Slot1 P3 with W2k.
Here a picture of HWinfo on the mashine. Still not installed the voodoo. I want first the CPU setup finished.
Maybe i found some day a SL4XY pair..

Honestly W2k is an under-rated operating system. its like a lean version of XP.

But the best thing for speed is the sata ssd. The ram also helps, but 2k will fly on anything with >256mb of ram. Even using pentium pro chips, the system feels good with 2K. provided you have the ram. ^.^

I would not worry about TRIM for the SSD - unless you are planning on using this machine every day, its not an issue. You can just keep a backup image of the drive if the worst happens, but honestly its a 1 in a million chance if you are using a quality name brand SSD.

Next step will be sleeving the ATX power adapter. Will try it tomorrow.
First fit test of the voodoo inside. Looks like it was made to be exatly on this board 😀.

This is shaping up to be one sexy build. Even that rear support bracket looks good.
I also agree Win2k feel's more correct for this era hardware then XP.

On my dual slot 1 I run Win2k. it feels a lot like Win9x and runs the vast majority of games just fine.
I do dual boot with Win98 just for those few games that don't like 2k

Was the original problem only that the motherboard's original BIOS was unable to detect both CPUs correctly (SL4XU & SL49P), but they still both worked in W2K at 700 MHz? Was W2K feeling slow before your BIOS upgrade, or only after? Does it still feel slow with just one CPU installed? Does the secondary slot require a terminator card?

Do you have a pair of coppermine based slot 2 Xeons to test, e.g. 1000/133/256K/2.8V, albeit at only 750 MHz?

I will relay some of my experience from when I setup a dual Slot 2 Xeon on a Dell Precision Workstation 610. Some of your issues feel similar to my exerpiences and the end result wasn't all balloons and cheers.

First off, running a pair of SL3CF CPUs worked fine. They are 550/100/2M/2.8V cartridges based on the Tanner core. The problems started when I tried running 700/100/2M or 700/100/1M cartridges (Cascades core). The jumper speed setting on my motherboard only officially went up to 550 MHz, however there are two reserved jumpers which, as it turns out, relate to 600 and 650 MHz.

I am able to run a single 700/100/2M/2.8V SL49R CPU without issue, provided I set the 650 MHz jumper. The CPU only runs with a 6.5x, however, so 650 MHz. If I install both SL49R CPUs, the BIOS screen stays blank. I also tried with a pair of SL49P (700/100/1M), but the screen stayed blank.

If I tried to install a pair of SL3WV (866/133/256k/2.8V) and set the jumper to 650 MHz, the system does power on, unlike with a pair of 700/100 cartridges, however I am displayed an unfortunate error:

1Alert! Processor cache size mismatch. Install like processors or one processor and a terminator card. System halted.

However, a single SL3WV (866/133/256k/2.8V) cartridge works just fine. The same conditions manifested when SL4HE (1000/133/256k/2.8V) cartridges were used.

I hope your issue is solely related to differing S-spec parts, however on my system, I vaguely recall testing a pair of PII or PIII Xeons (at 550 MHz or less) with differing S-specs and it was functional.

The slowdowns come when i plugged in both CPUs. I will get today the matching CPU. Will see if this was really the issue they dont like each other.
The bios update itself changed nothing on that. But it was worth doing it because my board was new with an very old release.
Yes, in my board manual is written that i need to install the dummy if i run single cpu.

Far as i know my board did not support FSB133. And someone correct me if im wrong, but the 256K xeons are just normal PIIIs in xeon package.
Im not really interested to install them. I want Cascades!

For Pentium3 there are no need to set jumper for the Speed (my board dont have any jumper for FSB or Speed).
I can set speed on bios but pretty sure its just for a PII setup.

edit:
got the CPU installed. It has the same CPU ID as the first one and on boot all errors gone.
But system is slow again. So i did a bios reset. After that the errors came back. And i always tryed retest CPU first.

Fan solution for the second CPU:

for the Sound an Audigy 2 ZS

I think i know whats going on. Here the first message after a bios reset:

It disable the cache! When i than switch to bios its shown 256k, but it musst be 1MB.

But the disabled L2 would be explain the system goes so slow.
Question is why the cache getting disabled when i plug in the second CPU?
Error 8121 is not listed in the manual..

Don’t feel bad. I have a few of the Intel dual processor server motherboards and they are very finicky about hardware.
And bios firmware. Keep at it and good luck. Looks great anyways.
I think Windows 2000 or Linux would be your best bet.

Intel486dx33 wrote on 2025-05-22, 14:51:

Don’t feel bad. I have a few of the Intel dual processor server motherboards and they are very finicky about hardware.
And bios firmware. Keep at it and good luck. Looks great anyways.
I think Windows 2000 or Linux would be your best bet.

You think downgrade the bios version is a good idea to try out?

Jackhead wrote on 2025-05-22, 14:57:

Intel486dx33 wrote on 2025-05-22, 14:51:

Don’t feel bad. I have a few of the Intel dual processor server motherboards and they are very finicky about hardware.
And bios firmware. Keep at it and good luck. Looks great anyways.
I think Windows 2000 or Linux would be your best bet.

You think downgrade the bios version is a good idea to try out?

You might want to read the release notes provided with each bios version to see if it would help with your hardware components.

atm i think like feipoa say, end is 550MHz dual for the board/bios.

Jackhead wrote on 2025-05-22, 21:27:

atm i think like feipoa say, end is 550MHz dual for the board/bios.

Sorry to be the harbinger of disappointment.

I even tried to overclock my 550's to 600 MHz, but they couldn't cope much past booting into DOS. Luckily, you didn't dish out for the 900/100/2M/2.8V chips.

The coppermine-based 1000/133/256K chips will work at 100 MHz, but with the reduced cache, you just as well be running a slot 1 machine. I was only curious if your board would let you go dual with 1000/133/256 chips with L2 enabled.

feipoa wrote on 2025-05-22, 23:29:

Sorry to be the harbinger of disappointment. […]
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Jackhead wrote on 2025-05-22, 21:27:

atm i think like feipoa say, end is 550MHz dual for the board/bios.

Sorry to be the harbinger of disappointment.

I even tried to overclock my 550's to 600 MHz, but they couldn't cope much past booting into DOS. Luckily, you didn't dish out for the 900/100/2M/2.8V chips.

The coppermine-based 1000/133/256K chips will work at 100 MHz, but with the reduced cache, you just as well be running a slot 1 machine. I was only curious if your board would let you go dual with 1000/133/256 chips with L2 enabled.

if you can even find those chips... The supply of those unicorns have disappeared like a fart in the wind...

There's no practical reason a 700mhz chip shouldn't work with a bios update. apparently intel never updated it for its own board? I wouldn't give up yet.

luckybob wrote on 2025-05-22, 23:56:

There's no practical reason a 700mhz chip shouldn't work with a bios update. apparently intel never updated it for its own board? I wouldn't give up yet.

Why provide a free BIOS update when you can sell the customer a new motherboard?

i found something releated to the L2 problems on some releasenotes.
Looks like serval builds try to fix the L2.
There was a microcode update for the 500/550 and the 450.

and :

Bug fix for L2 Cache Reg not set
correctly problem found on NS
corruption

no idea what "NS" means..

1C440GX+ BIOS 3.0 Release Notes
2Note:  BIOS 3.0 must be used with BMC firmware verstion 1.03 (CYMBC13.ZIP). 
36/16/1999
4
5*************************************************************************************
6
7BLD    Date       C440GX+              ECO L440GX+         L440GX+ Production Release
8----------------------------------------------------------------------
965    5/27/99    Production Release 3.0
10                1. Based on BUILD 64
11                2. Banner roll for P3.0 build 65
12
1364    5/17/99    Release  P2.1
14                1. Based on BUild 59
15                2. Changes for WIN 2K with 2Gig of memory
16
17
18
1963    5/14/99   Beta release for Candidate P3.0
20                 1. added WIN 2K 2Gig fix. 
21                 2. Added additional feature for loging
22                    errors on Flash Parameter block
23                 3. DMI Vital Data Protection 
24                 4. New Adaptec BIOS              
25                 5. Bug fix for L2 Cache Reg not set
26                     correctly problem found on NS 
27                     corruption 
28
2962    5/14/99                         Beta 2.0 release for Candidate P7.0
30                                        1. Based on BUILD 60
31                                        2. added WIN 2K 2Gig fix. 
32                                        3. Added additional feature for loging
33                                           errors on Flash Parameter block
34                                           corruption 
35
3661    5/12/99                         Release 6.1
37                                        1. Based on BUILD 58  does not include DMI fix
38                                        2. added WIN 2K 2Gig fix. 
39
4060    5/11/99                         Beta 1.0 release for Candidate P7.0
41                                        1. DMI Vital Data Protection 
42                                        2. New Adaptec BIOS           
43                                        3. PEP minor string fix up       
44                                        4. Bug fix for L2 Cache Reg not set
45                                            correctly problem 
46 
4759    4/29/99    ECO Release  P2.0
48                 Same as Build 56 with roll banner for production 2.0
49
5058    4/20/99                         Release  P6.0
51                                        roll banner for production 6.0
5257    4/20/99                         Beta release for Candidate P6.0
53                                        Added new Microcode Patch for C0 673        
54
55
56
57         
5856    4/13/99   Beta release for Candidate P2.0
59                1. Added fix for User Bin not being removed from Runtime
60                        memory

61                2. Added fix for logging SERR in SEL         
62                3. Added fix for Type 1,2,3 more robust and  
63                   type 6 and type 17 for > 512 Memory fix   
64                4. Added string fix for PEP Black out period 
65                5. Fix PEP string for number of min Black out time
66                6. Added fixes for the C0 stepping cache initialization
67                
68         
6955    4/12/99                         Beta release for Candidate P6.0         
70                                      1. Added fix for clocking 550Mhz processor   
71                                      2. Added fix for logging SERR in SEL         
72                                      3. Added fix for Type 1,2,3 more robust and  
73                                         type 6 and type 17 for > 512 Memory fix   
74                                      4. Added string fix for PEP Black out period 
75                                      5. Added fixes for the C0 stepping cache initialization
76
77
78
79
8054    3/17/99   C440GX+ ECO PEP Beta release
81                PEP Feature added
82
8353    3/11/99                        Production Release L440GX+ P5.0 
84
8552    3/04/99   PRoduction Release C440GX+ P1.0 
86                1. Banner roll for Production Release 1.0
87                2. Buffer strength change from L440GX+ 
88
8951    3/02/99                          N/A L440GX+ ECO Slot 1 related changes                                              
9050    3/01/99                          Bad Build                                               
91
92
9349    2/26/99   RC3 C440GX+ for P1.0 
94                 1. Fix for SMBIOS DMI data where the Cache 
95                        info is switched per processor 
96                        fixed int 15 DA92
97                 2. Reverse the order of the slot for the 
98                        error logging on DIMM 
99                 3. Banner change from L/C to C 
100                 4. IDE performance  changes 
101                 5. Fix for First Time Boot 
102                 6. P6 Microcode update for CPUID 673
103                 7. Fix for EMP Access mode not saved when EMP password
104                        entered 
105                 8. No PEP features in Setup
106                
107
10848	2/22/99	   RC Beta for C440GX+ ECO PEP
109                    1 added prechare for the DEC bridge 
110                        for 66Mhz PCI cards
111                    2 Fix for the PCI IRQ APIC routing table.  
112                    3 fix for SMBIOS DMI data where the 
113                        cache infor is switched per 
114                        processor    
115                    4 Fix PEP Send Test Page feature 
116                        was not sending pages 
117                    5 Enabled PEP features
11847	2/16/99		                                Production Release 4.0
11946	2/12/99		                                RC 5 - Trans for Japanese PSN
12045	2/11/99	        RC 1 for P5.0 L440GX+ ECO
121                    1. Enabled PEP features
122                    2. Reverse the order of the 
123                       slot for the error logging 
124                       on DIMM 
125                    3. Added translations for 
126                       the PSN setup	
12744	2/11/99		                                RC 4 -Translations for PSN Fix
12843	2/11/99		                                RC 3 - Reverse the order of the 
129                                                        slot for the error logging on DIMM
13042	2/11/99	        C440GX+ RC2 for P1.0
131                    1. Added PIIX4 precharging code to 
132                        avoid long IDE drive detection
133                    2. Change to BIOS ID to C440GX
134                    3. No PEP features	
13541	2/09/99		                                RC 2 -Added PIIX4 precharging code 
136                                                        to avoid long IDE drive detection
13740	2/09/99		                                RC 1- 
138                                                        1 Added processor serial number 
139                                                          PSN en/disable option to Setup. 
140                                                        2 DMI type 6 and type 17 handler bug
141                                                          Correctly interpret size word 
142                                                          returned by chipset
143
14439	2/07/99	        C440GX+ RC1 for P1.0
145                    1 added feature for displaying locked 
146                        processors in setup.
147                    2 Fix for DMI Cache string on C440GX+. 
148                    3 Fix for CPU step and cache INFO in setup
149                    4 Added bit for locked processors in setup 
150                      and added Post CPU speed for locked 
151                      processors in setup 
152                    5 Added new string and node for CPU speed at post 
153                    6 Added processor serial number PSN en/disable 
154                      option to Setup. 
155                    7 DMI type 6 and type 17 handler bug
156                      Correctly interpret size word returned 
157                      by chipset
158                    8 Added work a round to check if using unbuffered 
159                      Dimms and double sided memory in >2 slots . 
160                      Buffer strength optimization
161                    9 No PEP features	
16238	2/02/99		                                Roll Banner for Production Release 3.0
16337	1/29/99	        C440GX+ Beta  for P1.0
164                    1. set the Piix4 IDE for optimal 
165                        values     
166                    2. Fix the quiet boot setup option for 
167                        if there is a logo present.    
168                    3. Added support for handling multiple 
169                        slots (1,2) and multiple CPU 
170                        types  
171                    4. Added DMI pentium III and Pentium II 
172                        strings.  New DMI structures were added 
173                    5. Fix for the HSBP information sometimes 
174                        not showing up  
175                    6. No PEP features
176  
17736	1/27/99	        L440GX+ ECO  
178                    1. Fix for Slot 1 and Slot 2 CPU updates
179                   	
18035	1/20/99		                                Production Release 2.0
181                                                    1. Fix for NT4.0 Greater than 1 gig 
182                                                        memory (wrong Microcode)
183                                                    2. Pentium III string change and 
184                                                        copyright 
18534	1/19/99	        L440GX+ ECO/ C440GX+ Beta for P1.0 
186                    1. Fix DMI processor swap for Proc 1 
187                        and Proc 2 on C440GX+. 
188                    2. Fix for S1 with L440GX+ from previous 
189                        S1 removeal on C440GX+ 
190                    3. Fix for CPU speed on setup menu. 
191                        Remove for C440GX+
192                    4. No PEP  features
193  
19433	1/15/99	        L440GX+ ECO /C440GX+ Beta P1.0
195                    Fix build error from Build 32	
19632	1/15/99	        Do not USE - L440GX+ ECO /C440GX+ Beta P1.0
197                    1. Pentium III string  added  
198                        and change Copyright 1999
199                    2. No PEP  features	
20031	1/14/99	        L440GX+ ECO /C440GX+ Beta P1.0
201                    1. change copyright year 1999
202                    2.  Pentium(R) III 
203                        Xeon(TM) or Pentium(R) II Xeon(TM)  
204                        swap DMI processor information for proc
205                    3. Remove S1 sleep state if C440GX+ 
206                    4. Set devices behind bridge
207                    5. Hide speed control in setup on C440GX+ 
208                        since this is done in FW
209                    6. Int15h-DA20, func 9Ch to exit if C440GX+ 
210                        platform detected.
211                    7. No PEP  features
212  
21330	1/05/99	        L440GX+ ECO PEP
214                    Based on Production 1.0 LW
215                    Added PEP features	
21629      12/18/99		                        Production Release 1.0 LW
217

Does anyone know how a Cascades 700/100/2M differs from a Tanner 550/100/2M, aside from the smaller manufacturing process of 0.18 um vs. 0.25 um?

I assumed that the Tanner core was largely a Katmai with a lot more cache at full speed, but I'm not able to place the Cascades. Was the Cascades a Coppermine with a lot more cache?

I assume cascades is coppermine with add cache, yes.

tryed some more tests.
With both CPUs installed bootet into win2k HWinfo show no L2 on second CPU.
That would equal with the first bios error that L2 is deactivated when second CPU is installed.
System is really slow but works absolute fine.

Jackhead wrote on 2025-05-23, 11:27:

With both CPUs installed bootet into win2k HWinfo show no L2 on second CPU.
That would equal with the first bios error that L2 is deactivated when second CPU is installed.
System is really slow but works absolute fine.

Why is the system really slow if only the secondary CPU has its cache disabled? If you set the affinity to 0 instead of 0,1 does it speed up? Or do you think the slow speed is due to some mutual hangup between CPU 1 and CPU2 cache as the system tries to arbitrate?

i definitely think its a bios/microcode problem.
With one cascades CPU it still did the L2 bios Reg not correctly, but windows dont care.
In Dual mode now way.
I also tryed switching win from ACPI to MPS and used MPS 1.1 or 1.4 in the bios.

I would say running the board with one cascades 900MHz and would be better as 2x 550 ?
Because i see no other options.

The 900mhz chips are unobtanium... sadly. I haven't seen a hit on my ebay saved searches in years.

There's a small probability that the 1000/133/256K cascades will work in dual, but they are 7.5x only, so 750 MHz. 550 MHz with 2M is more interesting.

I remember seeing one 900/2M/2.8V five years ago on eBay. I thought I bought it, but when I looked in my box of Xeons, it wasn't there. I think your best bet to obtain one is to make a trade deal with a CPU collector.