Reply 960 of 963, by vsharun
RayeR wrote on 2025-08-26, 16:01:I wouldn't mix SMM/ME to this (but yes, in some case it is possible IO port trapping in SMM to emulate some legacy stuff like port 64h of keyboard via USB HID).
For simplicity, there are various bridges on the path from CPU to ISA device (on modern system multiple ones), e.g. CPU2PCIE -> PCIE2PCI -> PCI2LPC/ISA. Every bridge can be configured to positive decode some IO windows (IO addres ranges) that are passed through to other side or not or can have subtractive decode that pass all IO address that are not claimed by some other devices on the bus. Problem is that generally bridges has limited number of configurable IO windows with some additional conditions like address alignment/granularity/minimum range... and there can be only one bridge with subtractive decode in the system (multiple ones would cause conflict as it couldn't be decided to which one pass the IO transaction). So this bridges routing capabilities may not be flexible enough for our purpose. As some legacy devices (timer, interrupt ctl, KBD...) are still in PCH and it's needed to pass IO transaction to them while we have our ISA bridge that needs to pass some other IO ranges (like for DMA controller, SB ports, PnP ports) so sometimes it may be impossible to split this 2 paths for onboard legacy devices and our ISA device. In a case where PCH wouldn't contain ANY legacy device it could then simple use one subtractive decode for all legacy ports to our device which would handle/emulate all that legacy devices (like times, interrupt ctl, etc...).
I would. SMM can easily trap port for no obvious reason.
BTW I heard that CHIPSEC has functionality of SMM traps dump via BIOS dump, or may check which ports within given range are trapped using performance counters: trapped port will generate SMI which a) leaves traces in SMI counter and b) has different (significantly higher) execution time.