Your motherboard was manufactured by Magtron Technology Co (based on the BIOS ID string).

The results are more or less what I expected and what other users on the forum has also found.
Overall, you'll notice that there isn't a vast speed improvement over the standard Cyrix DLC CPU (since the TI CPU is actually a Cyrix DLC CPU but, with just 8K of L1 cache).

It would be interesting to see how each CPU compares on the Doom 1 Timedemo 3 benchmark but, with an ET4000AX ISA card, I suspect that you will have a bottleneck there. If you can find a "hybrid" 3/486 motherboard with VLB slots (with a VLB graphics card) then it would be interesting to see the performance comparison.

Still, I find the Cyrix/TI DLC & TI SXL CPU's very interesting.
So much that, back in 1993, I actually bought a Cyrix 486DLC-40 with its Cyrix math co-processor, instead of an Intel 486DX-33.

The grey-topped Cyrix FasMath FPU's are a smidge faster than the black-top ones. Someone mentioned that the black-top FPUs changed something to increase compatibility at the small expensive of performance. Landmark is sensitive enough to see the difference in speed. Unfortunately, the grey-tops don't usually work with the SXL when clock doubling is enabled.

Awesome thread! I have a PGA 132 version of the 486 SXL (9413FTB1 4031854). I recently read this website: https://x86.fr/the-uca-now-supports-ti486s-fe … sting-ti486sxl/ where the guy says an SXL 40 can be clock doubled by enabling a register if it's a B0 stepping. I have no idea if this applies to the 386 vintage but it sounds like it might.

A more general question I have is, other than this SXL-40, is there anything better for a 33MHz 386 setup? I mean if you can't change the crystal? I would obviously want to overclock the SXL2 but Feipoa says you can't do that. Maybe the silicon is no good. Then I heard there was a 33/66 with interposer in the works but I guess that's not done yet. So is there anything better for what I have now? I want to keep the bus speed high and the cache high for maximum benefit to the bottlenecked 386 and it seems the SXL-40 is the ticket. But it can't hurt to ask if there's something better.

You can use an SXL2, but you may need a black-topped or DLC type Cyrix FasMath when clock doubling. This may also depend on if you are using SCSI; I no longer recal the details. More info here: Re: Register settings for various CPUs The SXL2 is set to 1x by default. Use DOS software to set 2x. You will need to experiment with the math co-processor selection.

The SXL2-66/80 interposer board has been sufficiently finished for some time and it works well. Assembly may not be for everyone though. Evergreen and Powerleap also made an SXL2-66 interposer. Evergreen used the QFP chip while Powerleap used the PGA.

You can use a clock tripled IBM Blue Lightning BL3 at 66, 80, or 100 MHz. There are various upgrade options, from Evergreen to IODATA and Buffalo. Some photos in this thread: 386 upgrade kits and the Transcomputer 486HPi - Am5x86-160 anyone?

Sometimes the logic on this BL3 boards gets in the way of it working properly, so you may also want to take a BL3 chip and solder it to a 386DX QFP-to-PGA interposer, as shown here: Creating a voltage regulated 386 BL3 module from existing parts Some people also run at 5V and bypass the 3.3V.

Yes, you can change the crystal oscillator on your 386 board. You'd use a 66 MHz crystal oscillator for a 33 MHz FSB, an 80 MHz crystal for a 40 MHz FSB, etc. You can also make variable crystal oscillators, e.g.
386 Clock Generator Replacement
Re: Project: Full Can Clock Oscillator Replacement

The fastest upgrade options for a 386 are:

1) using a Transcomputer upgrade module with an Am5x86 at 160 MHz
2) using an IBM Blue Lightning BL3 upgrade module at 2x50 MHz or 3x33 MHz
3) using the custom PGA-168 to PGA-132 interposer PCB with SXL2-66 at up to 90 MHz (2x45). Nearly all CPU samples can run at 80 MHz with the right voltage.
4) use a Cyrix DRx2-66

Some 386 boards tend to be optimal with the BL3, like the SiS Rabbit, while others have benchmark numbers skew in favour of the SXL2 (Symphony Haydn II).

Thanks for the reply! Well in my case, I would prefer not to change the crystal (yet) because I don't want to take any risks on my only 386. However I am a bit confused. You say I can use an SXL2 (perhaps insinuating that a crystal change would be necessary) but in another thread you said something like if you were in Vegas you'd put all your money on the SXL2 not being able to OC from 25 to 33 MHz (I'm paraphrasing). Similarly in the transcomputer thread you linked you said you tried to OC an IIT x2 and it wouldn't go up by more than 2 MHz???? I believe you but wtf?! I've seen Atheatos oc an intel 386 25MHz chip to 50+ with no problems (100% OC) and he also got just about every FPU from 40MHz to 55MHz. But neither the SXL2 nor the IIT X2 can overclock by even 10%? So they made their single clock chips out of gold and their double clock chips out of dog turds? I guess I just don't understand enough about overclocking or chip fabrication or something. I guess the 33/66 with interposer is my only option currently but even that's not a drop-in and I'm assuming I can't buy it fully assembled.

The SXL-40 is still a very nice chip and paired with a Cyrix it'll put up a fight but I really wanted to leverage the FPU clock doubling without dropping the bus speed since that seems to be the weak point of these systems.

Also to answer your question about SCSI, the DMA causes a cache flush, basically nerfing the benefit of the on-chip cache and crippling the chip's performance. That's what I read when doing my FPU research.

A crystal swap is pretty trivial. The majority aren't soldered onto the motherboard.

You are confusing the FSB speed versus the clock doubled speed. An SXL2-50 runs at 2x25 MHz, or 50 MHz. It will not clock to 2x33 MHz, or 66 MHz. From memory, the SXL2-50 can run at up to about 55 MHz (2x27.5 Mhz) with a small heatsink/fan. You may be able to get 60 MHz with a peltier and cherry picking the best silicon. If you have 8 race horses running around a track, they don't all finish at the same time. Some horses can run faster than their peers, just as some CPUs samples of the same model will over clock higher. To go faster on an SXL2, you need a die shrink, but they are in QFP and PGA-168 formats.

An Intel 386 25 MHz doesn't have any L1 cache. If you want to run the SXL2 with the L1 cache disabled, you may be able to clock it slightly higher.

If you want a drop-in replacement with clock doubling, find an SXL2-50 and an IIT x2 and run them at 50 MHz with a crystal oscillator swap. I don't recall if the IIT x2 can do 55 MHz. Or run an SXL-40 at 40 MHz with a FasMath copro.

Not all cache invalidation approaches negate the benefit of the L1 cache w/scsi + SXL. I have an SXL2 running at 90 Mhz with SCSI and it runs well. This was discussed in depth starting here: Re: Register settings for various CPUs but if you don't have the background understanding, it might not make sense.

feipoa wrote on 2026-08-22, 01:11:

A crystal swap is pretty trivial. The majority aren't soldered onto the motherboard. […]
Show full quote

A crystal swap is pretty trivial. The majority aren't soldered onto the motherboard.

Mine unfortunately is and while I've seen it done plenty on youtube and it seems quite doable, I've been down that road before and without the training and experience, I just don't trust myself. You only get one chance to screw up.

You are confusing the FSB speed versus the clock doubled speed. An SXL2-50 runs at 2x25 MHz, or 50 MHz. It will not clock to 2x33 MHz, or 66 MHz. From memory, the SXL2-50 can run at up to about 55 MHz (2x27.5 Mhz) with a small heatsink/fan. You may be able to get 60 MHz with a peltier and cherry picking the best silicon. If you have 8 race horses running around a track, they don't all finish at the same time. Some horses can run faster than their peers, just as some CPUs samples of the same model will over clock higher. To go faster on an SXL2, you need a die shrink, but they are in QFP and PGA-168 formats.

I probably am confusing something. I understand manufacturing variation (I work in manufacturing myself) but I don't get why clock doubling has anything to do with it. % is %. A 386-40 can overclock 10% or a P2 with a 10x multiplier can overclock 10%. I'd think the thermal and electrical overload would be the same. I could be wrong, I just don't understand why. I also didn't know that cache made the chip hotter. The IIT doesn't have any cache on it. Probably just a PLL I'm assuming? So why the 40mhz single clock can OC to 55 but the clock doubled 25 can only do 27 just doesn't make intuitive sense to me. I get that it's effectively 50 -> 54 but again, that seems trivial. It is what it is, I just find it confusing.

An Intel 386 25 MHz doesn't have any L1 cache. If you want to run the SXL2 with the L1 cache disabled, you may be able to clock it slightly higher.

Interesting. Again I didn't realize the cache somehow did something to the load.

If you want a drop-in replacement with clock doubling, find an SXL2-50 and an IIT x2 and run them at 50 MHz with a crystal oscillator swap. I don't recall if the IIT x2 can do 55 MHz. Or run an SXL-40 at 40 MHz with a FasMath copro.

If I do anything it will probably be to put the adjustable oscillator in there and then de-clock to 25. That seems like the best option because at least that way I can OC the ISA bus to compensate for the depressed FSB. The only thing I guess I can't compensate for is the bus latency between the CPU and FPU, so every floating point instruction fetch will be slow as hell and will have to rely on the chip internals to make up for that.

Not all cache invalidation approaches negate the benefit of the L1 cache w/scsi + SXL. I have an SXL2 running at 90 Mhz with SCSI and it runs well. This was discussed in depth starting here: Re: Register settings for various CPUs but if you don't have the background understanding, it might not make sense.

Oh I'm not claiming that it doesn't work. I'm just saying I read that SCSI devices and sound cards can be problematic because their DMA causes a cache flush. That's literally all I know about it. I was just prompting you because you said your memory was hazy on the subject. Seems it wasn't that hazy after all 😜

Hang on, maybe I just realized what you were trying to say. Take the IIT FPU for example. Are you saying that the design itself is like a glass of water with a capacity of 55...whatever and whether it's a single clock going from 40 --> 55 or a double clock going from 2 x 25 --> 2 x 27.5, it's the same max capacity that is bottlenecking both chips? Like due to the manufacturing process or whatever? So when they made the x2 chip they didn't start with a clean slate and set nominal to 2 x 25 + a healthy tolerance? It was the same 40 mhz target + its healthy tolerance, just geared differently, so now the chip is eating into that tolerance to give you 50? Like if you started with a 6.2L V8 and chopped the block off to make a 4L engine out of it but then ran it as a 2-stroke so it put out the same as an 8L? And then asking why it can't put out another 10% on top of that? Because that would make more sense... and would mean the designers tried to scrape more performance out of an existing design by eating into their own tolerance...

There's no tolerances as such, it's all the same design but how it comes out the oven varies. Due to the manufacturing process (nanometre size) a common yield is 75-90% usable chips. The best chips are given the highest speed rating.

Most FPUs aren't able to run faster than 40MHz, and that's also a good bus clock for RAM & Cache speed, and you can run the ISA clock at 20MHz. It's a good level of performance across the board. Everything becomes iffy between 40-50MHz bus clock.

Double clocking a CPU from 40 to 80MHz only speeds up the L1 cache, and then waits for the rest of the system.

And that's why I originally bought the SXL-40 for my 33 machine. Even if I change the crystal to 25 so it works on both clock doubled parts (SXL2 and IIT x2), the problem is that most applications that use FPU avoid the expensive instructions anyway and Cyrix's chip is fast enough that several instructions are bottlenecked by the CPU's BIU, not the execution unit on the chip. So if I cut the bus speed and double the FPU execution speed, in some cases I gain nothing and actually lose. Division and sqrt will get faster but adds and muls will get slower because they're waiting on the bus to retire anyway. So a lot of upgrade paths produce a horribly imbalanced scenario (Check Retrotechbyte's blue lightning video where he ran Quake) where you have this nuclear integer performance and horrendous FPU performance combo. I think 40Mhz single clock or 33/66 is much much better than going down to 25 even at a 3x/4x multiplier. Unfortunately I'm learning now that the IIT x2 can't handle 33... which really sucks.

Well. I put in my IIT x2 and ran it with the turbo button off (so 33/2 cpu and 33 FPU) and that ran fine, albeit shitty so I decided to ride the lightning and I hit the turbo button and it worked. Not only did it work but I played quake demo3 on it to completion and it was 0.2FPS faster. So it seems you can OC a 25/50 IIT to 33/66 just by dropping it into a 33mhz system and doing nothing else.

It would run even faster if you would replace the CPU with DLC / DXr2 / SLX. The CPU has more overall influence then FPU. Even in FPU intensive tasks like AutoCAD.

i played around with this a few years ago.

I found that using the cyrix cache tool was very helpul at raising benchmark scores for tests that have a larger memory footprint. So does the size of the motherboard cache. Doom has a much larger memory footprint print than the synthetic benchmarks from that time.

Re: 486DLC cache coherency blues and headaches

Looks like your on chip cache is enabled which is nice. Still, you might be able to get a little bit faster playing with the settings on the cyrix.exe tool, but that all depends on the interaction with your motherboard chipset.

Increasing your ISA bus speed by lowering your bus divider can also improve a lot of real world performance scores like Doom or Winbench that depend on disk or graphics performance. It might not affect synthetic bechmarks or fpu benchmarks marks though.

douglar wrote on 2026-08-26, 10:16:

Looks like your on chip cache is enabled which is nice. Still, you might be able to get a little bit faster playing with the settings on the cyrix.exe tool, but that all depends on the interaction with your motherboard chipset.

Sorry I'm a bit confused. All I did was drop a clock doubled IIT into a normal 386-33 system. My cache is just board L2 cache as there's none on the 386 or the FPU that I'm aware of. I do want to pair it with an SXL2 but I guess the point is I was going to do all this at my default bus speed of 33 so it would be an OC for both chips and I was under the impression this wouldn't work. Seems it does for the IIT. So might it also be true for the SXL?

Run the Quake benchmark a four times back-to-back. Does it crash and do you always get the same score? Quake generally isn't the best FPU benchmark for systems this slow. Try some AutoCAD renderings. On my system, I also test mp3 decompression.

It is unlikely that you will get sustained reliable performance out of an IIT 487DLX25/50 FPU at 66 Mhz when paired with an SXL2-66 or DRX2-66. You may find the dynamics change a bit when using a CPU with L1 cache enabled. I had a few samples of IIT x2 and tried to get the 66 MHz configuration stable on multiple motherboards. I was only able to achieve stability at 66 Mhz when using a ULSI Math-Co DX-2 66 FPU.

Since you are wishing to maintain a 33 MHz FSB, and are looking for turn-key, your best bet is to use a DRx2-66 paired with a Cyrix black-top FasMath. The benefit of running clock doubled FPU's, e.g. ULSI 66 MHz, compared to a Cyrix FasMath at 33 MHz is very minimal. Refer to this brief benchmarking thread: A brief comparison of 386 FPUs

Gahhhrrrlic wrote on 2026-08-26, 11:14:

Sorry I'm a bit confused. All I did was drop a clock doubled IIT into a normal 386-33 system. My cache is just board L2 cache as there's none on the 386 or the FPU that I'm aware of. I do want to pair it with an SXL2 but I guess the point is I was going to do all this at my default bus speed of 33 so it would be an OC for both chips and I was under the impression this wouldn't work. Seems it does for the IIT. So might it also be true for the SXL?

My point was that 1) you might see some noticeable performance changes if you play the cyrix.exe tool with some different parameters for the caching that are just as large as swapping FPUs. And 2) real world tests tend to use larger memory regions than the DOS based synthetics, which makes things more sensitive to caching.

But thanks for doing the tests. I found it interesting and I appreciate that you took the time to do them.

Here is an interesting link: https://www.ardent-tool.com/CPU/Cyrix_Cx486.html

feipoa wrote on 2026-08-26, 12:07:

Refer to this brief benchmarking thread: https://www.ebay.com/itm/257697319654

Looks like a Cut & Pasta error ?

douglar wrote on 2026-08-26, 18:52:

Looks like a Cut & Pasta error ?

Thanks. Fixed it!

feipoa wrote on 2026-08-26, 12:07:

It is unlikely that you will get sustained reliable performance out of an IIT 487DLX25/50 FPU at 66 Mhz when paired with an SXL2-66 or DRX2-66. You may find the dynamics change a bit when using a CPU with L1 cache enabled. I had a few samples of IIT x2 and tried to get the 66 MHz configuration stable on multiple motherboards. I was only able to achieve stability at 66 Mhz when using a ULSI Math-Co DX-2 66 FPU.

I suspect you are right about that. If the huge gains in FP performance I have seen from simply adding L1 cache are attributable to reduced bus latency, wait states, whatever then the duty of the chip ought to be much higher. I might be getting away with it now because I'm not getting the full potential out of the chip. But my personal goal here is to first try and get my computer as fast as possible without making any modifications to it and also keeping it truly a 386. If I could run a hybrid chip clock doubled at 33 bus speed I would consider it as a future upgrade path but right now going from 2000 whetstones to 3000 whetstones is pretty awesome as a drop-in and I dare say it removes the FP bottleneck of the 386 at 33MHz (I understand 3000 whet is not a lot in absolute terms but it's not going to hold a 386-33 back)

My point was that 1) you might see some noticeable performance changes if you play the cyrix.exe tool with some different parameters for the caching that are just as large as swapping FPUs. And 2) real world tests tend to use larger memory regions than the DOS based synthetics, which makes things more sensitive to caching.

But thanks for doing the tests. I found it interesting and I appreciate that you took the time to do them.

Here is an interesting link: https://www.ardent-tool.com/CPU/Cyrix_Cx486.html

Oh 100%. Everything I've seen in all my research so far, including this OP indicates that L1 cache makes a massive difference in both the CPU and FPU. I will keep screwing around with this X2 chip to see how it performs in all the benchmarks and in Quake. It's just too bad these chips are so rare. Not only do they make excellent companions for the hybrid chips (if clocked correctly) but even in a basic 386 system like mine, I really appreciate the 50% bump.

I'm not sure how the L1 cache improves FPU performance. This can't be tested easily as with it enabled the CPU performance increases and this increase will also improve the FPU benchmarks.