Chkcpu wrote on 2025-06-11, 14:24:

Hi byte_76, […]
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byte_76 wrote on 2025-06-09, 16:57:

Hi Jan, […]
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Chkcpu wrote on 2025-06-09, 14:19:

Hi byte_76, […]
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Hi byte_76,

Great to hear the patched BIOS works as planned! 😀

However, getting the L1 cache in WB mode is another matter.
The Am5x86 article on my website, that you found earlier, also contains information on how to find the jumper that is connected to the CPU’s WB/WT# pin B-13.

A first step is connecting this pin to Vcc to get the L1 cache in WB, but this will most certainly crash the PC. As you see from the article, a lot of other conditions need to be fulfilled as well, one of which concerns the BIOS.
The 1994 BIOS has only WB enable logic for the Cx486DX(2) and Intel 486DX2WB (P24D), so it doesn’t program the chipset for L1 WB support on any other CPU model, when you set WB in the BIOS Setup.

So another BIOS patch is required, but this will need a full BIOS analysis. Success on this is slim however, as Ali 1429(G) chipset documentation is not available. Also the P24D jumper settings on this board are needed to know how to connect the HITM#, INV, and CACHE# signals between the chipset and CPU.

Not a project with a reasonable chance of success. But when I can find the time, I like to analyze this 1429G chipset L1 WB logic to at least contribute to @Rav’s Universal chipset patcher. project.

Let me know if you ever find the B870 board’s manual with P24D jumper settings. That would help enormously!

Jan

Hi Jan,

I think it is unlikely that I will ever find the manual for this board because it is not a very common board.

I have identified the jumper pin for B-13 but there is no 3.3v or 5V directly next to it. There is however 5.1V on a jumper pin nearby. (eg. if B-13 is jumper pin 1 then 5V is jumper pin 3 and pin 2 does not seem to be connected)

The board currently displays WB cache in CHKCPU when I install my Cyrix DX2-v66 and I think it also previously displayed WB when I installed my AMD DX4-100 SV8B but now it only indicates WT with that CPU.

Should I go ahead and connect jumper B-13 to the 5.1V pin? (Is it not risky to put 5V on that pin? I mean even the CPU voltage is only 3.3V and I'd rather not fry my CPU)

Hi byte_76,

The Am5x86 datasheet specifies this 3.45V Vcore CPU with 5V tolerant I/O. Apart from the supply voltage pins, the absolute maximum voltage on any pin is specified as Vcc +2.6V. So as long as you stay below 6.0V on pin B-13, you should be safe.

When you are going ahead with this L1 cache WB test on the Am5x86, try booting from a DOS 5 or 6 floppy. This is the best L1 cache WB coherency test I know, on any WB capable CPU.

Cheers, Jan

Hi Jan,

I have connected pin B-13 to the 5V pin.

I confirmed in your CHKCPU app that it does now indicate that the cache is configured in Write-Back mode.

I haven't had time to search for a floppy disk as I usually just use my Gotek drive which does not want to work with this board.

Other tools from Phil's benchmark suite do run without any issues. (Booted from an SD card with DOS 6.22)

byte_76 wrote on 2025-06-10, 08:13:

That’s interesting. How different is your board? Can you post a pic? […]
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PC Hoarder Patrol wrote on 2025-06-09, 18:51:

Believe these boards were commonly used in Brother / Kyodai BCR series PCs in the early-mid 90's which might be another route to a manual...I have an older version of the B870-II with an April 93 BIOS which came as part of such a system, but that board only supports uo to P24T class processors (no ob voltage reg & no manual 🙁 )

That’s interesting. How different is your board? Can you post a pic?

Maybe you can add the voltage regulator and any other components that are missing.

I’ve shared the original BIOS from my board earlier in the thread, and to TRW if you want to download it.

Sorry for the crap pic...it's the only one I have to hand till I dig the system out of storage & properly document it for TRW. Can't really tell at this point if a VRM could be retrofitted, but my old initial 2019 inventory notes tell me the board model is SXCPCB870A1 and the BIOS rev. / string is BROTHER REV.C / 40-0215-001241-001011-040493-ALI1429-F

I had some time to play around with the machine yesterday and it seems that my enthusiasm may have been a bit premature.

In 4x clock mode, the performance is strange or inconsistent. (Speedsys in particular)

With cache in WT mode, the system scores the following:

4x Clock Mode (133MHz):

Speedsys - 13.75
Doom 640x480 - 36.83 fps
PC Player 640x480 - 6.0
Quake 640x480 - 11.5
3D Bench - 58.1
Chris's 3D Bench - 18.3 (10.9 fps)

3x Clock Mode (100MHZ)

Speedsys - 37.78
Doom 640x480 - 33.30 fps
PC Player 640x480 - 5.5
Quake 640x480 - 10 fps
3D Bench - 58.3
Chris's 3D Bench - 17.2 (10.3 fps)

The system has these components:

8MB RAM
Chips DSP6430 VLB display card
2GB MicrosSD boot drive with DOS 6.22
Goldstar ISA IO controller card (Prime 2 chip)

What are your thoughts. Do these results seem to be a bit lower than expected?

byte_76 wrote on 2025-06-14, 08:48:

4x Clock Mode (133MHz): Speedsys - 13.75 .... What are your thoughts. Do these results seem to be a bit lower than expected? […]
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4x Clock Mode (133MHz):
Speedsys - 13.75
....
What are your thoughts. Do these results seem to be a bit lower than expected?

I'd expect an Speedsys score >= 44 for a well configured 486 4x @ 133 Mhz w/ WT
I'd expect an Speedsys score >= 49 for a well configured 486 4x @ 133 Mhz w/ WB

Speedsys = 13.75 is more in line with a 486 4x @ 133 Mhz with the cache disabled.

Perhaps you are running into something like this where the benchmark is ending up in a non-cacheable region of RAM?

Re: Benchmark discrepancies after loading DOS high or using himem

Are you loading Himem.sys? Are you using the fast A20 gate in the BIOS?

Yes, I agree that the Speedsys results seem to indicate that cache is disabled, however the other results, while not great, are fast enough to cast doubt on that conclusion..

I am not using himem.sys.
The Gate A20 only has two options which is Normal and Fast. I have it set on Fast.

I'm using exactly the same settings for 3x clock mode which does perform much better in Speedways.

I noticed that. Speedsys was certainly and outlier here.

While it was more of a cyrix 486slc thing, it is possible that there is a small area of memory that isn’t cached. Speedsys is a small benchmark. Maybe it fell into a small uncached area, while the larger benchmarks like doom and quake straddle it and are less affected?

Try loading dos high and seeing if that moves things around. Try running from a dos session under windows. That would definitely move things around.

Is there a tool that can test to see if different regions of memory are performing differently?

byte_76 wrote on 2025-06-12, 16:52:

Hi Jan, […]
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Chkcpu wrote on 2025-06-11, 14:24:

Hi byte_76, […]
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byte_76 wrote on 2025-06-09, 16:57:

Hi Jan, […]
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Hi Jan,

I think it is unlikely that I will ever find the manual for this board because it is not a very common board.

I have identified the jumper pin for B-13 but there is no 3.3v or 5V directly next to it. There is however 5.1V on a jumper pin nearby. (eg. if B-13 is jumper pin 1 then 5V is jumper pin 3 and pin 2 does not seem to be connected)

The board currently displays WB cache in CHKCPU when I install my Cyrix DX2-v66 and I think it also previously displayed WB when I installed my AMD DX4-100 SV8B but now it only indicates WT with that CPU.

Should I go ahead and connect jumper B-13 to the 5.1V pin? (Is it not risky to put 5V on that pin? I mean even the CPU voltage is only 3.3V and I'd rather not fry my CPU)

Hi byte_76,

The Am5x86 datasheet specifies this 3.45V Vcore CPU with 5V tolerant I/O. Apart from the supply voltage pins, the absolute maximum voltage on any pin is specified as Vcc +2.6V. So as long as you stay below 6.0V on pin B-13, you should be safe.

When you are going ahead with this L1 cache WB test on the Am5x86, try booting from a DOS 5 or 6 floppy. This is the best L1 cache WB coherency test I know, on any WB capable CPU.

Cheers, Jan

Hi Jan,

I have connected pin B-13 to the 5V pin.

I confirmed in your CHKCPU app that it does now indicate that the cache is configured in Write-Back mode.

I haven't had time to search for a floppy disk as I usually just use my Gotek drive which does not want to work with this board.

Other tools from Phil's benchmark suite do run without any issues. (Booted from an SD card with DOS 6.22)

Hi byte_76,

I’ve made progress with analyzing the ATC-1762 BIOS and found the L1 cache WB logic in the VER-2.0 BIOS.
It appears that the “Internal Cache WB/WT” option in the BIOS (CHIPSET FEATURES SETUP menu) only works on the Pentium Overdrive 63/83 (P24T), Cyrix Cx486S(2), and Cx486DX(2) CPUs. On all other CPUs, this setting is simply ignored and the BIOS programs the chipset for L1 WT mode then.
So not even the i486DX2WB (P24D) is supported in WB mode.

I found that the Ali1429(G) chipset’s L1 WB mode support is Enabled by setting register 19h bits 4 and 2 to “1”. This is true for both Cyrix and Intel CPUs and I’ve found no distinction between the Cyrix and Intel L1 WB logic in this Award BIOS. And why there need to be 2 bits set for WB and cleared for WT mode, I can only guess.
I’ve confirmed this L1 WB logic in your original Mecer B870 AMI WinBIOS (works only on the Cx486S/DX) and in the Phoenix BIOS of the DataExpert EXP4349 board. They all work the same way on these two register bits.

I’ve now made a further ATC-1762 patch J.2 BIOS, where I changed the “Internal Cache WB/WT” option in the BIOS to work also on the Am5x86, Am486DX4WB, i486DX4WB, and P24D (i486DX2WB) CPUs. Note that this is not an automatic function and you have to set the BIOS to match the L1 WB jumper setting on the board.

In addition I’ve added a proper “Am5x86” CPU Type display when running this CPU in x4 multiplier mode and corrected the Speed display to 133MHz when a 4x33 setting is used.
And of course the y2094 bug and 2GB limit bug fixes from the patch J.1 BIOS are also present in this patch J.2 version.

Here is the new ATC-1762 patch J.2 BIOS:

Now that you found the L1 WB jumper and the BIOS is fixed to enable the chipset’s L1 WB protocol, the remaining question is if the board has the proper connections of the HITM# and CACHE# signals between the chipset and CPU, either via jumpers or directly. I hope the later, so you can enjoy proper L1 cache WB support on your B870 board.

I will keep my fingers crossed. 😉
Enjoy, Jan

Chkcpu wrote on 2025-07-22, 14:01:

Hi byte_76, […]
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byte_76 wrote on 2025-06-12, 16:52:

Hi Jan, […]
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Chkcpu wrote on 2025-06-11, 14:24:

Hi byte_76, […]
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Hi byte_76,

The Am5x86 datasheet specifies this 3.45V Vcore CPU with 5V tolerant I/O. Apart from the supply voltage pins, the absolute maximum voltage on any pin is specified as Vcc +2.6V. So as long as you stay below 6.0V on pin B-13, you should be safe.

When you are going ahead with this L1 cache WB test on the Am5x86, try booting from a DOS 5 or 6 floppy. This is the best L1 cache WB coherency test I know, on any WB capable CPU.

Cheers, Jan

Hi Jan,

I have connected pin B-13 to the 5V pin.

I confirmed in your CHKCPU app that it does now indicate that the cache is configured in Write-Back mode.

I haven't had time to search for a floppy disk as I usually just use my Gotek drive which does not want to work with this board.

Other tools from Phil's benchmark suite do run without any issues. (Booted from an SD card with DOS 6.22)

Hi byte_76,

I’ve made progress with analyzing the ATC-1762 BIOS and found the L1 cache WB logic in the VER-2.0 BIOS.
It appears that the “Internal Cache WB/WT” option in the BIOS (CHIPSET FEATURES SETUP menu) only works on the Pentium Overdrive 63/83 (P24T), Cyrix Cx486S(2), and Cx486DX(2) CPUs. On all other CPUs, this setting is simply ignored and the BIOS programs the chipset for L1 WT mode then.
So not even the i486DX2WB (P24D) is supported in WB mode.

I found that the Ali1429(G) chipset’s L1 WB mode support is Enabled by setting register 19h bits 4 and 2 to “1”. This is true for both Cyrix and Intel CPUs and I’ve found no distinction between the Cyrix and Intel L1 WB logic in this Award BIOS. And why there need to be 2 bits set for WB and cleared for WT mode, I can only guess.
I’ve confirmed this L1 WB logic in your original Mecer B870 AMI WinBIOS (works only on the Cx486S/DX) and in the Phoenix BIOS of the DataExpert EXP4349 board. They all work the same way on these two register bits.

I’ve now made a further ATC-1762 patch J.2 BIOS, where I changed the “Internal Cache WB/WT” option in the BIOS to work also on the Am5x86, Am486DX4WB, i486DX4WB, and P24D (i486DX2WB) CPUs. Note that this is not an automatic function and you have to set the BIOS to match the L1 WB jumper setting on the board.

In addition I’ve added a proper “Am5x86” CPU Type display when running this CPU in x4 multiplier mode and corrected the Speed display to 133MHz when a 4x33 setting is used.
And of course the y2094 bug and 2GB limit bug fixes from the patch J.1 BIOS are also present in this patch J.2 version.

Here is the new ATC-1762 patch J.2 BIOS:

The attachment AT1762J2.zip is no longer available

Now that you found the L1 WB jumper and the BIOS is fixed to enable the chipset’s L1 WB protocol, the remaining question is if the board has the proper connections of the HITM# and CACHE# signals between the chipset and CPU, either via jumpers or directly. I hope the later, so you can enjoy proper L1 cache WB support on your B870 board.

I will keep my fingers crossed. 😉
Enjoy, Jan

Hi Jan,

This was quite unexpected. I thought maybe you had moved on to other projects.

Thank you so much for the new patched BIOS, I'm looking forward to testing it.
I'll provide feedback here as soon as I have. (Unfortunately won't have time before the weekend but I'll post as soon as I can)

I'm sure this took quite some hours of work. I really appreciate all the time and effort that you spent on it.
Since it is such an unusual board, I really hope that you're at least able to use the learnings to help others as well.

Chkcpu wrote on 2025-07-22, 14:01:

Hi byte_76, […]
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byte_76 wrote on 2025-06-12, 16:52:

Hi Jan, […]
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Chkcpu wrote on 2025-06-11, 14:24:

Hi byte_76, […]
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Hi byte_76,

The Am5x86 datasheet specifies this 3.45V Vcore CPU with 5V tolerant I/O. Apart from the supply voltage pins, the absolute maximum voltage on any pin is specified as Vcc +2.6V. So as long as you stay below 6.0V on pin B-13, you should be safe.

When you are going ahead with this L1 cache WB test on the Am5x86, try booting from a DOS 5 or 6 floppy. This is the best L1 cache WB coherency test I know, on any WB capable CPU.

Cheers, Jan

Hi Jan,

I have connected pin B-13 to the 5V pin.

I confirmed in your CHKCPU app that it does now indicate that the cache is configured in Write-Back mode.

I haven't had time to search for a floppy disk as I usually just use my Gotek drive which does not want to work with this board.

Other tools from Phil's benchmark suite do run without any issues. (Booted from an SD card with DOS 6.22)

Hi byte_76,

I’ve made progress with analyzing the ATC-1762 BIOS and found the L1 cache WB logic in the VER-2.0 BIOS.
It appears that the “Internal Cache WB/WT” option in the BIOS (CHIPSET FEATURES SETUP menu) only works on the Pentium Overdrive 63/83 (P24T), Cyrix Cx486S(2), and Cx486DX(2) CPUs. On all other CPUs, this setting is simply ignored and the BIOS programs the chipset for L1 WT mode then.
So not even the i486DX2WB (P24D) is supported in WB mode.

I found that the Ali1429(G) chipset’s L1 WB mode support is Enabled by setting register 19h bits 4 and 2 to “1”. This is true for both Cyrix and Intel CPUs and I’ve found no distinction between the Cyrix and Intel L1 WB logic in this Award BIOS. And why there need to be 2 bits set for WB and cleared for WT mode, I can only guess.
I’ve confirmed this L1 WB logic in your original Mecer B870 AMI WinBIOS (works only on the Cx486S/DX) and in the Phoenix BIOS of the DataExpert EXP4349 board. They all work the same way on these two register bits.

I’ve now made a further ATC-1762 patch J.2 BIOS, where I changed the “Internal Cache WB/WT” option in the BIOS to work also on the Am5x86, Am486DX4WB, i486DX4WB, and P24D (i486DX2WB) CPUs. Note that this is not an automatic function and you have to set the BIOS to match the L1 WB jumper setting on the board.

In addition I’ve added a proper “Am5x86” CPU Type display when running this CPU in x4 multiplier mode and corrected the Speed display to 133MHz when a 4x33 setting is used.
And of course the y2094 bug and 2GB limit bug fixes from the patch J.1 BIOS are also present in this patch J.2 version.

Here is the new ATC-1762 patch J.2 BIOS:

The attachment AT1762J2.zip is no longer available

Now that you found the L1 WB jumper and the BIOS is fixed to enable the chipset’s L1 WB protocol, the remaining question is if the board has the proper connections of the HITM# and CACHE# signals between the chipset and CPU, either via jumpers or directly. I hope the later, so you can enjoy proper L1 cache WB support on your B870 board.

I will keep my fingers crossed. 😉
Enjoy, Jan

Hi Jan,

I have spent about an hour testing the new patched BIOS and I can confirm that the CPU is displayed correctly at boot and in your CHKCPU application.

I've also confirmed that when I disconnect the jumper for L1 WB, the system correctly indicates WT but when the jumper is connected it indicates WB. (BIOS settings configured to match)

The performance of the system seems good but Speedsys only scores 13.35 points for the CPU test. The L1 and L2 cache size is indicated correctly in Speedsys though.
All the other benchmarks on Phil's Dosbench pack are performing well, so the cache is probably working correctly.

That said, I have not compared the results of all the benchmarks in WT vs WB mode.

I am also able to confirm that my SD card is detected correctly as 8GB and seems to work without any issues.

Thank you once again for your hard work on this BIOS, I think this board is very useable in this state and performance is good considering that the board was never designed to run an AMD 5x86 P75.
There is potential for me to squeeze more out of this system now with this patched BIOS and I'm certainly going to do some tests when I have more time to play with it.

Please may you post a picture of the SpeedSys Cache chart (in both WB and WT mode)?
And how does floppy disk access work when operating the CPU in WB mode?